Intel IA-32 Manuale Utente
Vol. 3A 8-45
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
•
When RH is 1 and the logical destination mode is active in a system using a flat
addressing model, the Destination ID field must be set so that bits set to 1 identify
processors that are present and enabled to receive the interrupt.
addressing model, the Destination ID field must be set so that bits set to 1 identify
processors that are present and enabled to receive the interrupt.
•
If RH is set to 1 and the logical destination mode is active in a system using cluster
addressing model, then Destination ID field must not be set to 0xFF; the
processors identified with this field must be present and enabled to receive the
interrupt.
addressing model, then Destination ID field must not be set to 0xFF; the
processors identified with this field must be present and enabled to receive the
interrupt.
4.
Destination mode (DM) — This bit indicates whether the Destination ID field should be
interpreted as logical or physical APIC ID for delivery of the lowest priority interrupt. If
RH is 1 and DM is 0, the Destination ID field is in physical destination mode and only the
processor in the system that has the matching APIC ID is considered for delivery of that
interrupt (this means no re-direction). If RH is 1 and DM is 1, the Destination ID Field is
interpreted as in logical destination mode and the redirection is limited to only those
processors that are part of the logical group of processors based on the processor’s logical
APIC ID and the Destination ID field in the message. The logical group of processors
consists of those identified by matching the 8-bit Destination ID with the logical
destination identified by the Destination Format Register and the Logical Destination
Register in each local APIC. The details are similar to those described in Section 8.6.2,
“Determining IPI Destination.” If RH is 0, then the DM bit is ignored and the message is
sent ahead independent of whether the physical or logical destination mode is used.
interpreted as logical or physical APIC ID for delivery of the lowest priority interrupt. If
RH is 1 and DM is 0, the Destination ID field is in physical destination mode and only the
processor in the system that has the matching APIC ID is considered for delivery of that
interrupt (this means no re-direction). If RH is 1 and DM is 1, the Destination ID Field is
interpreted as in logical destination mode and the redirection is limited to only those
processors that are part of the logical group of processors based on the processor’s logical
APIC ID and the Destination ID field in the message. The logical group of processors
consists of those identified by matching the 8-bit Destination ID with the logical
destination identified by the Destination Format Register and the Logical Destination
Register in each local APIC. The details are similar to those described in Section 8.6.2,
“Determining IPI Destination.” If RH is 0, then the DM bit is ignored and the message is
sent ahead independent of whether the physical or logical destination mode is used.
8.11.2
Message Data Register Format
The layout of the Message Data Register is shown in Figure 8-25.