Intel IA-32 Manuale Utente

10-32 Vol. 3A

The examples in this section apply to processors that support a maximum physical address size
of 36 bits. The base and mask values entered in variable-range MTRR pairs are 24-bit values
that the processor extends to 36-bits. 

For example, to enter a base address of 2 MBytes (200000H) in the IA32_MTRR_PHYSBASE3
register, the 12 least-significant bits are truncated and the value 000200H is entered in the Phys-
Base field. The same operation must be performed on mask values. For example, to map the
address range from 200000H to 3FFFFFH (2 MBytes to 4 MBytes), a mask value of
FFFE00000H is required. Again, the 12 least-significant bits of this mask value are truncated,
so that the value entered in the PhysMask field of IA32_MTRR_PHYSMASK3 is FFFE00H.
This mask is chosen so that when any address in the 200000H to 3FFFFFH range is AND’d with
the mask value, it will return the same value as when the base address is AND’d with the mask
value (which is 200000H).

To map the address range from 400000H to 7FFFFFH (4 MBytes to 8 MBytes), a base value of
000400H is entered in the PhysBase field and a mask value of FFFC00H is entered in the Phys-
Mask field.

Here is an example of setting up the MTRRs for an system. Assume that the system has the
following characteristics:

•

96 MBytes of system memory is mapped as write-back memory (WB) for highest system
performance.

•

A custom 4-MByte I/O card is mapped to uncached memory (UC) at a base address of
64 MBytes. This restriction forces the 96 MBytes of system memory to be addressed from
0 to 64 MBytes and from 68 MBytes to 100 MBytes, leaving a 4-MByte hole for the I/O
card. 

•

An 8-MByte graphics card is mapped to write-combining memory (WC) beginning at
address A0000000H. 

•

The BIOS area from 15 MBytes to 16 MBytes is mapped to UC memory.