Intel IA-32 Manuale Utente

10-34 Vol. 3A

Caches 96-100 MByte as WB cache type.

IA32_MTRR_PHYSBASE3 =  0000 0000 0400 0000H
IA32_MTRR_PHYSMASK3 =  0000 00FF FFC0 0800H  
Caches 64-68 MByte as UC cache type.

IA32_MTRR_PHYSBASE4 =  0000 0000 00F0 0000H
IA32_MTRR_PHYSMASK4 =  0000 00FF FFF0 0800H  
Caches 15-16 MByte as UC cache type.

IA32_MTRR_PHYSBASE5 =  0000 0000 A000 0001H
IA32_MTRR_PHYSMASK5 =  0000 00FF FF80 0800H  
Caches A0000000-A0800000 as WC type.

The range that is to be mapped to a variable-range MTRR must meet the following “power of
2” size and alignment rules:

1.

The minimum range size is 4 KBytes, and the base address of this range must be on at least
a 4-KByte boundary.

2.

For ranges greater than 4 KBytes, each range must be of length 2

  and its base address

must be aligned on a 2

 boundary, where n is a value equal to or greater than 12. The base-

address alignment value cannot be less than its length. For example, an 8-KByte range
cannot be aligned on a 4-KByte boundary. It must be aligned on at least an 8-KByte
boundary.

If the MTRRs are not enabled (by setting the E flag in the IA32_MTRR_DEF_TYPE MSR),
then all memory accesses are of the UC memory type. If the MTRRs are enabled, then the
memory type used for a memory access is determined as follows:

1.

If the physical address falls within the first 1 MByte of physical memory and fixed MTRRs
are enabled, the processor uses the memory type stored for the appropriate fixed-range
MTRR.

2.

Otherwise, the processor attempts to match the physical address with a memory type set by
the variable-range MTRRs:

a.

If one variable memory range matches, the processor uses the memory type stored in
the IA32_MTRR_PHYSBASEn register for that range.

b.

If two or more variable memory ranges match and the memory types are identical,
then that memory type is used.

c.

If two or more variable memory ranges match and one of the memory types is UC, the
UC memory type used.