Intel IA-32 Manuale Utente
Vol. 3A 2-9
SYSTEM ARCHITECTURE OVERVIEW
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The GDTR, LDTR, and IDTR registers contain the linear addresses and sizes (limits) of
their respective tables. See also: Section 2.4, “Memory-Management Registers.”
their respective tables. See also: Section 2.4, “Memory-Management Registers.”
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The task register contains the linear address and size of the TSS for the current task. See
also: Section 2.4, “Memory-Management Registers.”
also: Section 2.4, “Memory-Management Registers.”
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Model-specific registers (not shown in Figure 2-1).
The model-specific registers (MSRs) are a group of registers available primarily to operating-
system or executive procedures (that is, code running at privilege level 0). These registers
control items such as the debug extensions, the performance-monitoring counters, the machine-
check architecture, and the memory type ranges (MTRRs).
system or executive procedures (that is, code running at privilege level 0). These registers
control items such as the debug extensions, the performance-monitoring counters, the machine-
check architecture, and the memory type ranges (MTRRs).
The number and function of these registers varies among different members of the IA-32
processor families. See also: Section 9.4, “Model-Specific Registers (MSRs),” and Appendix B,
“Model-Specific Registers (MSRs).”
processor families. See also: Section 9.4, “Model-Specific Registers (MSRs),” and Appendix B,
“Model-Specific Registers (MSRs).”
Most systems restrict access to system registers (other than the EFLAGS register) by application
programs. Systems can be designed, however, where all programs and procedures run at the
most privileged level (privilege level 0). In such a case, application programs would be allowed
to modify the system registers.
programs. Systems can be designed, however, where all programs and procedures run at the
most privileged level (privilege level 0). In such a case, application programs would be allowed
to modify the system registers.
2.1.6.1
System Registers in IA-32e Mode
In IA-32e mode, the four system-descriptor-table registers (GDTR, IDTR, LDTR, and TR) are
expanded in hardware to hold 64-bit base addresses. EFLAGS becomes the 64-bit RFLAGS
register. CR0-CR4 are expanded to 64 bits. CR8 becomes available. CR8 provides read-write
access to the task priority register (TPR) so that the operating system can control the priority
classes of external interrupts.
expanded in hardware to hold 64-bit base addresses. EFLAGS becomes the 64-bit RFLAGS
register. CR0-CR4 are expanded to 64 bits. CR8 becomes available. CR8 provides read-write
access to the task priority register (TPR) so that the operating system can control the priority
classes of external interrupts.
In 64-bit mode, debug registers DR0–DR7 are 64 bits. In compatibility mode, address-matching
in DR0-DR3 is also done at 64-bit granularity.
in DR0-DR3 is also done at 64-bit granularity.
On systems that support IA-32e mode, the extended feature enable register (IA32_EFER) is
available. This model-specific register controls activation of IA-32e mode and other IA-32e
mode operations. In addition, there are several model-specific registers that govern IA-32e
mode instructions:
available. This model-specific register controls activation of IA-32e mode and other IA-32e
mode operations. In addition, there are several model-specific registers that govern IA-32e
mode instructions:
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IA32_KernelGSbase — Used by SWAPGS instruction.
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IA32_LSTAR — Used by SYSCALL instruction.
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IA32_SYSCALL_FLAG_MASK — Used by SYSCALL instruction.
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IA32_STAR_CS — Used by SYSCALL and SYSRET instruction.