Intel IA-32 Manuale Utente
Vol. 3A 15-27
8086 EMULATION
6.
Loads the CS and EIP registers with values from the interrupt vector table entry pointed to
by the interrupt vector number. Only the 16 low-order bits of the EIP are loaded and the 16
high-order bits are set to 0. The interrupt vector table is assumed to be at linear address 0 of
the current virtual-8086 task.
by the interrupt vector number. Only the 16 low-order bits of the EIP are loaded and the 16
high-order bits are set to 0. The interrupt vector table is assumed to be at linear address 0 of
the current virtual-8086 task.
7.
Begins executing the selected interrupt handler.
An IRET instruction at the end of the handler procedure reverses these steps to return program
control to the interrupted 8086 program.
control to the interrupted 8086 program.
Note that with method 5 handling, a mode switch from virtual-8086 mode to protected mode
does not occur. The processor remains in virtual-8086 mode throughout the interrupt-handling
operation.
does not occur. The processor remains in virtual-8086 mode throughout the interrupt-handling
operation.
The method 5 handling actions are virtually identical to the actions the processor takes when
handling software interrupts in real-address mode. The benefit of using method 5 handling to
access the 8086 program handlers is that it avoids the overhead of methods 2 and 3 handling,
which requires first going to the virtual-8086 monitor, then to the 8086 program handler, then
back again to the virtual-8086 monitor, before returning to the interrupted 8086 program (see
Section 15.3.1.2, “Handling an Interrupt or Exception With an 8086 Program Interrupt or
Exception Handler”).
handling software interrupts in real-address mode. The benefit of using method 5 handling to
access the 8086 program handlers is that it avoids the overhead of methods 2 and 3 handling,
which requires first going to the virtual-8086 monitor, then to the 8086 program handler, then
back again to the virtual-8086 monitor, before returning to the interrupted 8086 program (see
Section 15.3.1.2, “Handling an Interrupt or Exception With an 8086 Program Interrupt or
Exception Handler”).
NOTE
Methods 1 and 4 handling can handle a software interrupt in a virtual-8086
task with a regular protected-mode handler, but this approach requires all
virtual-8086 tasks to use the same software interrupt handlers, which
generally does not give sufficient latitude to the programs running in the
virtual-8086 tasks, particularly MS-DOS programs.
task with a regular protected-mode handler, but this approach requires all
virtual-8086 tasks to use the same software interrupt handlers, which
generally does not give sufficient latitude to the programs running in the
virtual-8086 tasks, particularly MS-DOS programs.
15.3.3.5
Method 6: Software Interrupt Handling
Method 6 handling is enabled when the VME flag is set to 1, the IOPL value is less than 3, and
the bit for the interrupt or exception vector in the redirection bit map is set to 0. With method 6
interrupt handling, software interrupts are handled in the same manner as was described for
method 5 handling (see Section 15.3.3.4, “Method 5: Software Interrupt Handling”).
the bit for the interrupt or exception vector in the redirection bit map is set to 0. With method 6
interrupt handling, software interrupts are handled in the same manner as was described for
method 5 handling (see Section 15.3.3.4, “Method 5: Software Interrupt Handling”).
Method 6 differs from method 5 in that with the IOPL value set to less than 3, the VIF and VIP
flags in the EFLAGS register are enabled, providing virtual interrupt support for handling
class 2 maskable hardware interrupts (see Section 15.3.2, “Class 2—Maskable Hardware Inter-
rupt Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism”). These flags
provide the virtual-8086 monitor with an efficient means of handling maskable hardware inter-
rupts that occur during a virtual-8086 mode task. Also, because the IOPL value is less than 3
and the VIF flag is enabled, the information pushed on the stack by the processor when invoking
the interrupt handler is slightly different between methods 5 and 6 (see Table 15-2).
flags in the EFLAGS register are enabled, providing virtual interrupt support for handling
class 2 maskable hardware interrupts (see Section 15.3.2, “Class 2—Maskable Hardware Inter-
rupt Handling in Virtual-8086 Mode Using the Virtual Interrupt Mechanism”). These flags
provide the virtual-8086 monitor with an efficient means of handling maskable hardware inter-
rupts that occur during a virtual-8086 mode task. Also, because the IOPL value is less than 3
and the VIF flag is enabled, the information pushed on the stack by the processor when invoking
the interrupt handler is slightly different between methods 5 and 6 (see Table 15-2).