Intel IA-32 Manuale Utente
17-14 Vol. 3A
IA-32 ARCHITECTURE COMPATIBILITY
17.17.6.8
INVALID OPERATION EXCEPTION ON DENORMALS
An invalid-operation exception is not generated on the 32-bit x87 FPUs upon encountering a
denormal value when executing a FSQRT, FDIV, or FPREM instruction or upon conversion to
BCD or to integer. The operation proceeds by first normalizing the value. On the 16-bit IA-32
math coprocessors, upon encountering this situation, the invalid-operation exception is gener-
ated. This difference has no impact on existing software. Software running on the 32-bit x87
FPUs continues to execute in cases where the 16-bit IA-32 math coprocessors trap. The reason
for this change was to eliminate an exception from being raised.
denormal value when executing a FSQRT, FDIV, or FPREM instruction or upon conversion to
BCD or to integer. The operation proceeds by first normalizing the value. On the 16-bit IA-32
math coprocessors, upon encountering this situation, the invalid-operation exception is gener-
ated. This difference has no impact on existing software. Software running on the 32-bit x87
FPUs continues to execute in cases where the 16-bit IA-32 math coprocessors trap. The reason
for this change was to eliminate an exception from being raised.
17.17.6.9
ALIGNMENT CHECK EXCEPTIONS (#AC)
If alignment checking is enabled, a misaligned data operand on the P6 family, Pentium, and
Intel486 processors causes an alignment check exception (#AC) when a program or procedure
is running at privilege-level 3, except for the stack portion of the FSAVE/FNSAVE, FXSAVE,
FRSTOR, and FXRSTOR instructions.
Intel486 processors causes an alignment check exception (#AC) when a program or procedure
is running at privilege-level 3, except for the stack portion of the FSAVE/FNSAVE, FXSAVE,
FRSTOR, and FXRSTOR instructions.
17.17.6.10 SEGMENT NOT PRESENT EXCEPTION DURING FLDENV
On the Intel486 processor, when a segment not present exception (#NP) occurs in the middle of
an FLDENV instruction, it can happen that part of the environment is loaded and part not. In
such cases, the FPU control word is left with a value of 007FH. The P6 family and Pentium
processors ensure the internal state is correct at all times by attempting to read the first and last
bytes of the environment before updating the internal state.
an FLDENV instruction, it can happen that part of the environment is loaded and part not. In
such cases, the FPU control word is left with a value of 007FH. The P6 family and Pentium
processors ensure the internal state is correct at all times by attempting to read the first and last
bytes of the environment before updating the internal state.
17.17.6.11
DEVICE NOT AVAILABLE EXCEPTION (#NM)
The device-not-available exception (#NM, interrupt 7) will occur in the P6 family, Pentium, and
Intel486 processors as described in Section 2.5, “Control Registers,” Table 2-1, and Chapter 5,
“Interrupt 7—Device Not Available Exception (#NM).”
Intel486 processors as described in Section 2.5, “Control Registers,” Table 2-1, and Chapter 5,
“Interrupt 7—Device Not Available Exception (#NM).”
17.17.6.12 COPROCESSOR SEGMENT OVERRUN EXCEPTION
The coprocessor segment overrun exception (interrupt 9) does not occur in the P6 family,
Pentium, and Intel486 processors. In situations where the Intel 387 math coprocessor would
cause an interrupt 9, the P6 family, Pentium, and Intel486 processors simply abort the instruc-
tion. To avoid undetected segment overruns, it is recommended that the floating-point save area
be placed in the same page as the TSS. This placement will prevent the FPU environment from
being lost if a page fault occurs during the execution of an FLDENV, FRSTOR, or FXRSTOR
instruction while the operating system is performing a task switch.
Pentium, and Intel486 processors. In situations where the Intel 387 math coprocessor would
cause an interrupt 9, the P6 family, Pentium, and Intel486 processors simply abort the instruc-
tion. To avoid undetected segment overruns, it is recommended that the floating-point save area
be placed in the same page as the TSS. This placement will prevent the FPU environment from
being lost if a page fault occurs during the execution of an FLDENV, FRSTOR, or FXRSTOR
instruction while the operating system is performing a task switch.
17.17.6.13 GENERAL PROTECTION EXCEPTION (#GP)
A general-protection exception (#GP, interrupt 13) occurs if the starting address of a floating-
point operand falls outside a segment’s size. An exception handler should be included to report
these programming errors.
point operand falls outside a segment’s size. An exception handler should be included to report
these programming errors.