Intel IA-32 Manuale Utente
17-16 Vol. 3A
IA-32 ARCHITECTURE COMPATIBILITY
17.17.7.5
FUCOM, FUCOMP, AND FUCOMPP INSTRUCTIONS
When executing the FUCOM, FUCOMP, and FUCOMPP instructions, the 32-bit x87 FPUs
perform unordered compare according to IEEE Standard 754. These instructions do not exist on
the 16-bit IA-32 math coprocessors. The availability of these new instructions has no impact on
existing software.
perform unordered compare according to IEEE Standard 754. These instructions do not exist on
the 16-bit IA-32 math coprocessors. The availability of these new instructions has no impact on
existing software.
17.17.7.6
FPTAN INSTRUCTION
On the 32-bit x87 FPUs, the range of the operand for the FPTAN instruction is much less
restricted (| ST(0) | < 2
restricted (| ST(0) | < 2
63
) than on earlier math coprocessors. The instruction reduces the operand
internally using an internal
π/4 constant that is more accurate. The range of the operand is
restricted to (| ST(0) | <
π/4) on the 16-bit IA-32 math coprocessors; the operand must be reduced
to this range using FPREM. This change has no impact on existing software.
17.17.7.7
STACK OVERFLOW
On the 32-bit x87 FPUs, if an FPU stack overflow occurs when the invalid-operation exception
is masked, the FPU returns the real, integer, or BCD-integer indefinite value to the destination
operand, depending on the instruction being executed. On the 16-bit IA-32 math coprocessors,
the original operand remains unchanged following a stack overflow, but it is loaded into register
ST(1). This difference has no impact on existing software.
is masked, the FPU returns the real, integer, or BCD-integer indefinite value to the destination
operand, depending on the instruction being executed. On the 16-bit IA-32 math coprocessors,
the original operand remains unchanged following a stack overflow, but it is loaded into register
ST(1). This difference has no impact on existing software.
17.17.7.8
FSIN, FCOS, AND FSINCOS INSTRUCTIONS
On the 32-bit x87 FPUs, these instructions perform three common trigonometric functions.
These instructions do not exist on the 16-bit IA-32 math coprocessors. The availability of these
instructions has no impact on existing software, but using them provides a performance upgrade.
These instructions do not exist on the 16-bit IA-32 math coprocessors. The availability of these
instructions has no impact on existing software, but using them provides a performance upgrade.
17.17.7.9
FPATAN INSTRUCTION
On the 32-bit x87 FPUs, the range of operands for the FPATAN instruction is unrestricted. On
the 16-bit IA-32 math coprocessors, the absolute value of the operand in register ST(0) must be
smaller than the absolute value of the operand in register ST(1). This difference has impact on
existing software.
the 16-bit IA-32 math coprocessors, the absolute value of the operand in register ST(0) must be
smaller than the absolute value of the operand in register ST(1). This difference has impact on
existing software.
17.17.7.10 F2XM1 INSTRUCTION
The 32-bit x87 FPUs support a wider range of operands (–1 < ST (0) < + 1) for the F2XM1
instruction. The supported operand range for the 16-bit IA-32 math coprocessors is
(0
instruction. The supported operand range for the 16-bit IA-32 math coprocessors is
(0
≤ ST(0) ≤ 0.5). This difference has no impact on existing software.
17.17.7.11
FLD INSTRUCTION
On the 32-bit x87 FPUs, when using the FLD instruction to load an extended-real value, a
denormal-operand exception is not generated because the instruction is not arithmetic. The
denormal-operand exception is not generated because the instruction is not arithmetic. The