ARM R4 Manuale Utente

ARM DDI 0363E

4-57

ID013010

Table 4-38 shows how the bit values correspond with the address format for invalidate and clean 
operations.

The purpose of the Data Synchronization Barrier operation is to ensure that all outstanding 
explicit memory transactions complete before any following instructions begin. This ensures 
that data in memory is up to date before the processor executes any more instructions.

The Data Synchronization Barrier Register is:
•

a write-only operation

•

accessible in both User and Privileged mode.

To access the Data Synchronization Barrier operation, write CP15 with:

MCR p15, 0, <Rd>, c7, c10, 4 ; Data Synchronization Barrier operation

For more information about memory barriers, see the ARM Architecture Reference Manual.

The purpose of the Data Memory Barrier operation is to ensure that all outstanding explicit 
memory transactions complete before any following explicit memory transactions begin. This 
ensures that data in memory is up to date before any memory transaction that depends on it.

The Data Memory Barrier operation is:
•

write-only 

•

accessible in User and Privileged mode.

To access the Data Memory Barrier operation write CP15 with:

MCR p15, 0, <Rd>, c7, c10,5

; Data Memory Barrier Operation.

For more information about memory barriers, see the ARM Architecture Reference Manual.

The BTCM Region Register holds the base address and size of the BTCM. It also determines if 
the BTCM is enabled. 

The BTCM Region Register is:
•

a read/write register

•

accessible in Privileged mode only.

Figure 4-41 on page 4-58 shows the arrangement of bits in the register.

[31:5]

Address

Specifies the address to invalidate or clean

[4:0]

Reserved

SBZ