ARM R4 Manuale Utente
Events and Performance Monitor
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
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6.3
Performance monitoring registers
The performance monitoring registers are described in:
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6.3.1
c9, Performance Monitor Control Register
The Performance MoNitor Control (PMNC) Register controls the operation of the three count
registers, and the CCNT Register.
registers, and the CCNT Register.
The PMNC Register is:
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A read/write register.
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Always accessible in Privileged mode. The USEREN Register determines accessibility in
User mode, see c9, User Enable Register on page 6-15.
User mode, see c9, User Enable Register on page 6-15.
Figure 6-1 shows the bit arrangement for the PMNC Register.
Figure 6-1 PMNC Register format
Table 6-2 shows how the bit values correspond with the PMNC Register.
D C P E
IMP
31
11
6
4 3 2 1 0
IDCODE
N
10
Reserved
D
P
P
5
X
24 23
16 15
Table 6-2 PMNC Register bit functions
Bits Field
Function
[31:24]
IMP
Implementer code:
0x41
= ARM
[23:16]
IDCODE
Identification code:
0x14
= Cortex-R4
[15:11]
N
Specifies the number of counters implemented:
0x3
= three counters implemented
[10: 6]
Reserved
RAZ on reads, Should Be Zero or Preserved (SBZP) on writes
[5]
DP
Disable CCNT when prohibited, that is, when non-invasive debug is not enabled:
0 = Count is enabled in prohibited regions. This is the reset value.
1 = Count is disabled in prohibited regions.
0 = Count is enabled in prohibited regions. This is the reset value.
1 = Count is disabled in prohibited regions.