ARM R4 Manuale Utente

ARM DDI 0363E

6-9

ID013010

Table 6-3 shows how the bit values correspond with the CNTENS Register.

To access the CNTENS Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c12, 1 ; Read CNTENS Register
MCR p15, 0, <Rd>, c9, c12, 1 ; Write CNTENS Register

The CNTENS Register retains its value when the enable bit of the PMNC is clear, even though 
its settings are ignored.

The CouNT ENable Clear (CNTENC) Register disables any of the Performance Monitor Count 
Registers.

When reading this register, any enable that reads as 0 indicates the corresponding counter is 
disabled. Any enable that reads as 1 indicates the corresponding counter is enabled.

When writing this register, any enable written with a value of 0 is ignored, that is, not updated. 
Any enable written with a value of 1 clears the counter enable.

The CNTENC Register is:

•

A read/write register

•

Always accessible in Privileged mode. The User Enable Register determines accessibility 
in User mode, see c9, User Enable Register on page 6-15.

Figure 6-3 on page 6-10 shows the bit arrangement for the CNTENC Register.

C

31

3 2 1 0

Reserved

P2

P1

P0

Performance monitor

counter enables

Cycle count enable

[31]

C

Cycle counter enable set:
0 = disable
1 = enable.

[30:3]

Reserved

UNP on reads, SBZP on writes

[2]

P2

Counter 2 enable

[1]

P1

Counter 1 enable

[0]

P0

Counter 0 enable