ARM R4 Manuale Utente

ARM DDI 0363E

11-7

ID013010

The Vector Catch Register (VCR) sets breakpoints on exception vectors as instruction 
addresses.

0x080

c32

RW

DTRRX

0x084

c33

W

ITR

0x088

c34

RW

DSCR

0x08C

c35

RW

DTRTX

0x090

c36

W

DRCR

0x094-0x0FC

c37-c63

R

-

RAZ

0x100-0x11C

c64-c71

RW BVR

0x120-0x13C

c72-c79

R

-

RAZ

0x140-0x15C

c80-c87

RW

BCR

0x160-0x17C

c88-c95

R

-

RAZ

0x180-0x19C

c96-c103

RW

WVR

0x1A0-0x1BC

c104-c111

R

-

RAZ

0x1C0-0x1DC

c112-c119

RW

WCR

0x1E0-0x1FC

c120-c127

R

-

RAZ

0x200-0x2FC

c128-c191

R

-

RAZ

0x300

c192

R

OSLAR

Not implemented in this processor. Reads as zero.

0x304

c193

R

OSLSR

0x308

c194

R

OSSRR

Not implemented in this processor. Reads as zero.

0x30C

c195

R

-

RAZ

0x310

c196

RW

PRCR

0x314

c197

R

PRSR

0x318-0x7FC

c198-c511

R

-

RAZ

0x800-0x8FC

c512-575

R

-

RAZ

0x900-0xCFC

c576-c831

R

-

RAZ

0xD00

-

0xDFC

c832-c895

R

-

0xE00

-

0xE7C

c896-c927

R

-

RAZ

0xE80

-

0xEFC

c928-c959

-

-

0xF00-0xFFC

c960-c1023

-

-