ARM R4 Manuale Utente

ARM DDI 0363E

14-24

ID013010

This section describes the cycle timing for the 

RFE

 and 

SRS

 instructions.

These instructions:

•

return from an exception and save exception return state respectively

•

take one or two memory cycles depending on doubleword alignment first address 
location.

In all cases the base register is a Very Early Reg.

Table 14-19 shows the cycle timing behavior for 

RFE

 and 

SRS

 instructions.

RFEIA <Rn>

10

1

SRSIA #<mode>

1

1

RFEIA <Rn>

11

2

SRSIA #<mode>

2

2