ARM R4 Manuale Utente

ARM DDI 0363E

14-25

ID013010

This section describes the cycle timing behavior for the 

CLREX

, 

DMB

, 

DSB

, 

ISB

, 

LDREX

, 

LDREXB

, 

LDREXD

, 

LDREXH

, 

STREX

, 

STREXB

, 

STREXD

, 

STREXH

, 

SWP

, and 

SWPB

 instructions

In all cases the base register, Rn, is a Very Early Reg. Table 14-20 shows the synchronization 
instructions cycle timing behavior.

The synchronization instructions 

DMB

, 

DSB

, and 

ISB

 stall the pipeline for a variable number of 

cycles, depending on the current state of the memory system.

CLREX

1

-

-

LDREX <Rt>, [Rn]

1

1

2

LDREXB <Rt>, [Rn]

1

1

2

LDREXH <Rt>, [Rn]

1

1

2

LDREXD <Rt>, [Rn]

a

a. Address must be 64-bit aligned.

1

1

2

STREX <Rd>, <Rt>, [Rn]

1

1

2

STREXB <Rd>, <Rt>, [Rn]

1

1

2

STREXH <Rd>, <Rt>, [Rn]

1

1

2

STREXD <Rd>, <Rt>, <Rt2>, [Rn]

1

1

2

SWP <Rt>, <Rt2>, [Rn]

2

2

3

SWPB <Rt>, <Rt2>, [Rn]

2

2

3