ARM R4 Manuale Utente

Cycle Timings and Interlock Behavior

ARM DDI 0363E

14-27

ID013010

Non-Confidential, Unrestricted Access

14.17 SVC, BKPT, Undefined, and Prefetch Aborted instructions

This section describes the cycle timing behavior for

SVC

, Undefined instruction,

BKPT

and

Prefetch Abort.

In all cases the exception is taken in the Wr stage of the pipeline.

SVC

and most Undefined

instructions that fail their condition codes take one cycle. A small number of Undefined
instructions that fail their condition codes take two cycles. Table 14-22 shows the

SVC

BKPT

Undefined, prefetch aborted instructions cycle timing behavior.

Table 14-22 SVC, BKPT, Undefined, prefetch aborted instructions cycle timing behavior

Instruction

Cycles

SVC

(formerly

SWI

)

BKPT

Prefetch Abort

Undefined Instruction