ARM R4 Manuale Utente
Processor Signal Descriptions
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
A-7
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A.4
Interrupt signals, including VIC interface signals
Table A-3 shows the Interrupt signals including signals used on the VIC interface.
Table A-3 Interrupt signals
Signal
Direction
Clocking
Description
nFIQ
Input
CLKIN
a
Any
b
Fast interrupt
c
.
nIRQ
Input
Any
Normal interrupt
.
INTSYNCEN
Input
Tie-off
Tie HIGH if the interrupt inputs are asynchronous to CLKIN.
Tie LOW if the interrupt inputs are synchronous to CLKIN.
Tie LOW if the interrupt inputs are synchronous to CLKIN.
IRQADDRV
Input
CLKIN
d
Any
e
Indicates IRQADDR is valid.
IRQADDRVSYNCEN
Input
Tie-off
Tie HIGH if the IRQADDRV input from the VIC is
asynchronous to CLKIN.
Tie HIGH if the IRQADDRV input from the VIC is
synchronous to CLKIN.
asynchronous to CLKIN.
Tie HIGH if the IRQADDRV input from the VIC is
synchronous to CLKIN.
IRQADDR [31:2]
Input
-
Address of the IRQ. This signal must be stable when
IRQADDRV is asserted.
IRQADDRV is asserted.
IRQACK
Output
CLKIN
Acknowledges interrupt.
nPMUIRQ
Output
CLKIN
Interrupt request by Performance Monitor Unit (PMU).
a. When INTSYNCEN is tied LOW
b. When INTSYNCEN is tied HIGH
c. This signal is level-sensitive and must be held LOW until a suitable interrupt response is received from the processor.
d. When IRQADDRVSYNCEN is tied LOW
e. When IRQADDRVSYCNEN is tied HIGH
b. When INTSYNCEN is tied HIGH
c. This signal is level-sensitive and must be held LOW until a suitable interrupt response is received from the processor.
d. When IRQADDRVSYNCEN is tied LOW
e. When IRQADDRVSYCNEN is tied HIGH