ARM R4 Manuale Utente

ARM DDI 0363E

A-8

ID013010

This section describes the processor L2 interface AXI signals. For more information on 
Advanced Microcontroller Bus Architecture (AMBA) AXI signals see the AMBA AXI Protocol 
Specification.

 All the outputs listed in this section have their reset values during standby.

Table A-4 shows the AXI master port signals for the L2 interface. With the exception of the 
ACLKENM, all signals are only sampled or driven on CLKIN edges when ACLKENM is 
asserted, see AXI interface clocking on page 3-9 for more information.

Input

Clock enable for the AXI master port.

Write address channel

Output

Transfer start address.

Output

Write burst type.

Output

Provides decode information for outer attributes:
b0000 = Strongly Ordered.
b0001 = Device.
b0011 = Normal, Non-cacheable.
b0110 = Normal, Cacheable. write-through.
b1111 = Normal, Cacheable. write-back, write allocation.
b0111 = Normal, Cacheable. write-back, no write allocation.

 The AXI specification describes these encodings using the 
pre-ARMv6 terms such as cacheable-bufferable. These terms 
are equivalent to the ARMv6 memory-type descriptions such as 
Normal, Non-cacheable used here.

Output

The identification tag for the write address group of signals.

Output

Write transfer burst length. The transfer burst length range is 
from one to 16. A 4-bit binary value minus one determines the 
transfer burst length.

Output

Lock signal.

Output

Protection type. Only bit [0] is used from the 3-bit AXI bus.

Input

Address ready. The slave uses this signal to indicate that it can 
accept the address.

Output

Indicates the size of the transfer.

Output

Provides decode information for the write address channel. See 
Table 9-3 on page 9-5 for information about the encoding of this 
signal.