ARM R4 Manuale Utente

ARM DDI 0363E

A-10

ID013010

Table A-5 shows the AXI master port error detection signals. these signals are only generated if 
the processor is configured to include AXI bus parity. See Configurable options on page 1-13 
for more information.

Table A-6 shows the AXI slave port signals for the L2 interface. With the exception of the 
ACLKENS, all signals are only sampled or driven on CLKIN edges when ACLKENS is 
asserted, see AXI interface clocking on page 3-9 for more information.

Output

Provides decode information for the read address channel. See 
Table 9-3 on page 9-5 for information about the encoding of this 
signal.

Output

Indicates address and control are valid.

Read Data Channel

Input

Read Data.

Input

The identification tag for the read data group of signals.

Input

Indicates the last transfer in a read burst.

Output

Read ready signal indicating that the bus master can accept read 
data and response information.

Input

Read response.

Input

Indicates that read data is available.

Output

Parity bit for write address channel

Output

Parity bit for write data channel

Input

Parity bit for write response channel

Output

Parity bit for read address channel

Input

Parity bit for read data channel

Output

Parity error indication for read data (bit [1]) and write response 
(bit[0]) channels

Input

Clock enable for the AXI slave port.

Write Address Channel

Input

Transfer start address.