Toshiba Xeon 2.8GHz UPG3843W Manuale Utente

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UPG3843W
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 Intel® Xeon™ Processor with 512 KB L2 Cache
Datasheet
111
7.4.6.3
Status Register
The Status Register shown in 
 indicates which (if any) thermal value thresholds for the
processor core thermal diode have been exceeded. It also indicates if a conversion is in progress or
if an open circuit has been detected in the processor core thermal diode connection. Once set, alarm
bits stay set until they are cleared by a Status Register read. A successful read to the Status Register
will clear any alarm bits that may have been set, unless the alarm condition persists. If the
SM_ALERT# signal is enabled via the Thermal Sensor Configuration Register and a thermal diode
threshold is exceeded, an alert will be sent to the platform via the SM_ALERT# signal.
This register is read by accessing the RS Command Register.
Table 53.  SMBus Thermal Sensor Status Register
7.4.6.4
Configuration Register
The Configuration Register controls the operating mode (stand-by vs. auto-convert) of the SMBus
thermal sensor
 shows the format of the Configuration Register. If the RUN/STOP bit is
set (high) then the thermal sensor immediately stops converting and enters stand-by mode. The
thermal sensor will still perform analog to digital conversions in stand-by mode when it receives a
one-shot command. If the RUN/STOP bit is clear (low) then the thermal sensor enters auto-
conversion mode.
This register is accessed by using the thermal sensor Command Register: The RC command
register is used for read commands and the WC command register is used for write commands. See
Bit
Name
Reset State
Function
7 (MSB)
BUSY
N/A
If set, indicates that the device’s analog to digital converter is 
busy.
6
RESERVED
RESERVED
Reserved for future use
5
RESERVED
RESERVED
Reserved for future use
4
RHIGH
0
If set, indicates the processor core thermal diode high 
temperature alarm has activated.
3
RLOW
0
If set, indicates the processor core thermal diode low 
temperature alarm has activated.
2
OPEN
0
If set, indicates an open fault in the connection to the 
processor core diode.
1
RESERVED
RESERVED
Reserved for future use.
0 (LSB)
RESERVED
RESERVED
Reserved for future use.