Toshiba Xeon 2.8GHz UPG3843W Manuale Utente
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UPG3843W
Intel® Xeon™ Processor with 512 KB L2 Cache
112
Datasheet
Table 54. SMBus Thermal Sensor Configuration Register
7.4.6.5
Conversion Rate Registers
The contents of the Conversion Rate Registers determine the nominal rate at which analog to
digital conversions happen when the SMBus thermal sensor is in auto-convert mode. There are two
Conversion Rate Registers, RCR for reading the conversion rate value and WCR for writing the
value.
digital conversions happen when the SMBus thermal sensor is in auto-convert mode. There are two
Conversion Rate Registers, RCR for reading the conversion rate value and WCR for writing the
value.
shows the mapping between Conversion Rate Register values and the conversion
, the Conversion Rate Register is set to its default state of 02h
(0.25 Hz nominally) when the thermal sensor is powered up.
There is a ±30% error tolerance
between the conversion rate indicated in the conversion rate register and the actual conversion rate.
Table 55. SMBus Thermal Sensor Conversion Rate Registers
7.4.7
SMBus Thermal Sensor Alert Interrupt
The SMBus thermal sensor located on the processor includes the ability to interrupt the SMBus
when a fault condition exists. The fault conditions consist of: 1) a processor thermal diode value
measurement that exceeds a user-defined high or low threshold programmed into the Command
Register or 2) disconnection of the processor thermal diode from the thermal sensor. The interrupt
can be enabled and disabled via the thermal sensor Configuration Register and is delivered to the
baseboard via the SM_ALERT# open drain output. Once latched, the SM_ALERT# should only be
cleared by reading the Alert Response byte from the Alert Response Address of the thermal sensor.
The Alert Response Address is a special slave address shown in
when a fault condition exists. The fault conditions consist of: 1) a processor thermal diode value
measurement that exceeds a user-defined high or low threshold programmed into the Command
Register or 2) disconnection of the processor thermal diode from the thermal sensor. The interrupt
can be enabled and disabled via the thermal sensor Configuration Register and is delivered to the
baseboard via the SM_ALERT# open drain output. Once latched, the SM_ALERT# should only be
cleared by reading the Alert Response byte from the Alert Response Address of the thermal sensor.
The Alert Response Address is a special slave address shown in
. The SM_ALERT# will
Bit
Name
Reset State
Function
7 (MSB)
MASK
0
Mask SM_ALERT# bit. Clear bit to allow interrupts via
SM_ALERT# and allow the thermal sensor to respond to the
ARA command when an alarm is active. Set the bit to disable
interrupt mode. The bit is not used to clear the state of the
SM_ALERT# output. An ARA command may not be recognized
if the mask is enabled.
SM_ALERT# and allow the thermal sensor to respond to the
ARA command when an alarm is active. Set the bit to disable
interrupt mode. The bit is not used to clear the state of the
SM_ALERT# output. An ARA command may not be recognized
if the mask is enabled.
6
RUN/STOP
0
Stand-by mode control bit. If set, the device immediately stops
converting, and enters stand-by mode. If cleared, the device
converts in either one-shot mode or automatically updates on a
timed basis.
converting, and enters stand-by mode. If cleared, the device
converts in either one-shot mode or automatically updates on a
timed basis.
5:0
RESERVED
RESERVED
Reserved for future use.
Register Value
Conversion Rate (Hz)
00h
0.0625
01h
0.125
02h
0.25
03h
0.5
04h
1.0
05h
2.0
06h
4.0
07h
8.0
08h to FFh
Reserved for future use