Intel E3815 FH8065301567411 Scheda Tecnica
Codici prodotto
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2179
18.7.10
USB Status (USBSTS)—Offset 84h
This register indicates pending interrupts and various states of the Host Controller. The
status resulting from a transaction on the serial bus is not indicated in this register.
Software sets a bit to '0' in this register by writing a '1' to it (RW1C). Refer to
specification eXtensible Host Controller Interface for Universal Serial Bus (xHCI) for
additional information concerning USB interrupt conditions.
Access Method
2
0b
RW
Interrupter Enable (INTE):
This bit provides system software with a means of
enabling or disabling the host system interrupts generated by Interrupters. When this
bit is a 1, then Interrupter host system interrupt generation is allowed, i.e. the xHC shall
issue an interrupt at the next interrupt threshold if the host system interrupt
mechanism (e.g. MSI, MSIX, etc.) is enabled. The interrupt is acknowledged by a host
system interrupt specific mechanism.
When this register is exposed by a Virtual Function (VF), this bit only enables the set of
Interrupters assigned to the selected VF.
Power Well:
Core
1
0b
RW
Host Controller Reset (HCRST):
This control bit is used by software to reset the host
controller. The effects of this bit on the xHC and the Root Hub registers are similar to a
Chip Hardware Reset.
When software writes a 1 to this bit, the Host Controller resets its internal pipelines,
timers, counters, state machines, etc. to their initial value. Any transaction currently in
progress on the USB is immediately terminated. A USB reset shall not be driven on
USB2 downstream ports, however a Hot or Warm Reseta shall be initiated on USB3 Root
Hub downstream ports. PCI Configuration registers are not affected by this reset. All
operational registers, including port registers and port state machines are set to their
initial values. Software shall reinitialize the host controller, as described in the xHCI for
USB specification, in order to return the host controller to an operational state.
This bit is cleared to 0 by the Host Controller when the reset process is complete.
Software cannot terminate the reset process early by writing a 0 to this bit and shall not
write any xHC Operational or Runtime registers until while HCRST is 1. Note, the
completion of the xHC reset process is not gated by the Root Hub port reset process.
Software shall not set this bit to 1 when the HCHalted (HCH) bit in the USBSTS register
is a 0. Attempting to reset an actively running host controller may result in undefined
behavior. When this register is exposed by a Virtual Function (VF), this bit only resets
the xHC instance presented by the selected VF. Refer to the xHCI for USB specification
for more information.
Power Well:
Core
0
0b
RW
Run/Stop (RS):
•
•
1 = Run
•
0 = Stop
When set to a 1, the xHC proceeds with execution of the schedule. The xHC continues
execution as long as this bit is set to a 1. When this bit is cleared to 0, the xHC
completes any current or queued commands or TDs, and any USB transactions
associated with them, then halts. Refer to section 5.4.1.1 for more information on how
R/S shall be managed. The xHC shall halt within 16 ms. after software clears the Run/
Stop bit if the above conditions have been met. The HCHalted (HCH) bit in the USBSTS
register indicates when the xHC has finished its pending pipelined transactions and has
entered the stopped state. Software shall not write a 1 to this flag unless the xHC is in
the Halted state (i.e. HCH in the USBSTS register is 1). Doing so may yield undefined
results. Writing a 0 to this flag when the xHC is in the Running state (i.e. HCH = 0) and
any Event Rings are in the Event Ring Full state (refer to section 4.9.4) may yield
undefined resultsresult in lost events. When this register is exposed by a Virtual
Function (VF), this bit only controls the run state of the xHC instance presented by the
selected VF.
Power Well:
Core
Bit
Range
Default &
Access
Field Name (ID): Description