Intel E3815 FH8065301567411 Scheda Tecnica

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2181

The default value for this register is implementation dependent.

4

0b

RW/C

The xHC sets this bit to a 1 when any port has a change 

bit transition from a 0 to a 1. This bit is allowed to be maintained in the Aux Power well. 

Alternatively, it is also acceptable that on a D3 to D0 transition of the xHC, this bit is 

loaded with the OR of all of the PORTSC change bits. Refer to the xHCI for USB 

specification for more information. This bit provides system software an efficient means 

of determining if there has been Root Hub port activity. Refer to the xHCI for USB 

specification for more information. When this register is exposed by a Virtual Function 

(VF), the VMM determines the state of this bit as a function of the Root Hub Ports 

associated with the Device Slots assigned to the selected VF. Refer to the xHCI for USB 

specification for more information.

Core

3

0b

RW/C

The xHC sets this bit to 1 when the Interrupt Pending (IP) bit 

of any Interrupter transitions from 0 to 1. Refer to the xHCI for USB specification for 

usage information.  

Software that uses EINT shall clear it prior to clearing any IP flags. A race condition may 

occur if software clears the IP flags, then clears the EINT flag, and between the 

operations another IP 0 to '1' transition occurs. In this case, the new IP transition shall 

be lost.  

When this register is exposed by a Virtual Function (VF), this bit is the logical 'OR' of the 

IP bits for the Interrupters assigned to the selected VF. And it shall be cleared to 0 when 

all associated interrupter IP bits are cleared, i.e. all the VFs Interrupter Event Ring(s) 

are empty. Refer to the xHCI for USB specification for more information.

Core

2

0b

RW/C

The xHC sets this bit to 1 when a serious error is detected, 

either internal to the xHC or during a host system access involving the xHC module. (In 

a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, 

and PCI Target Abort.) When this error occurs, the xHC clears the Run/Stop (R/S) bit in 

the USBCMD register to prevent further execution of the scheduled TDs. If the HSEE bit 

in the USBCMD register is a 1, the xHC shall also assert out-of-band error signaling to 

the host. Refer to the xHCI for USB specification for more information.  

When this register is exposed by a Virtual Function (VF), the assertion of this bit affects 

all VFs and reflects the Host System Error state of the Physical Function (PF0). Refer to 

the xHCI for USB specification for more information.

Core

1

0b

RO

Reserved.

Core

0

1b

RO

This bit is a 0 whenever the Run/Stop (R/S) bit is a 1. The xHC sets 

this bit to 1 after it has stopped executing as a result of the Run/Stop (R/S) bit being 

cleared to 0, either by software or by the xHC hardware (e.g. internal error). If this bit is 

'1', then SOFs, microSOFs, or Isochronous Timestamp Packets (ITP) shall not be 

generated by the xHC, and any received Transaction Packet shall be dropped. When this 

register is exposed by a Virtual Function (VF), this bit only reflects the Halted state of 

the xHC instance presented by the selected VF. Refer to the xHCI for USB specification 

for more information.

Core

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 64 bits)

[B:0, D:20, F:0] + 10h