Freescale Semiconductor 56F8322 ユーザーズマニュアル
Device Description
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor
7
Preliminary
1.1.5
Energy Information
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Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
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On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories
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On-chip regulators for digital and analog circuitry to lower cost and reduce noise
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Wait and Stop modes available
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ADC smart power management
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Each peripheral can be individually disabled to save power
1.2 Device Description
The 56F8322 and 56F8122 are members of the 56800E core-based family of hybrid controllers. Each
combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the
functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective
solution. Because of their low cost, configuration flexibility, and compact program code, the 56F8322
and 56F8122 are well-suited for many applications. These devices include many peripherals that are
especially useful for automotive control (56F8322 only); industrial control and networking; motion
control; home appliances; general purpose inverters; smart sensors; fire and security systems; power
management; and medical monitoring applications.
combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the
functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective
solution. Because of their low cost, configuration flexibility, and compact program code, the 56F8322
and 56F8122 are well-suited for many applications. These devices include many peripherals that are
especially useful for automotive control (56F8322 only); industrial control and networking; motion
control; home appliances; general purpose inverters; smart sensors; fire and security systems; power
management; and medical monitoring applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code.
The instruction set is also highly efficient for C Compilers to enable rapid development of optimized
control applications.
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code.
The instruction set is also highly efficient for C Compilers to enable rapid development of optimized
control applications.
The 56F8322 and 56F8122 support program execution from internal memories. Two data operands can be
accessed from the on-chip data RAM per instruction cycle. These devices also provide one external
dedicated interrupt line and up to 21 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
accessed from the on-chip data RAM per instruction cycle. These devices also provide one external
dedicated interrupt line and up to 21 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
1.2.1
56F8322 Features
The 56F8322 hybrid controller includes 32KB of Program Flash and 8KB of Data Flash, each
programmable through the JTAG port, and 4KB of Program RAM and 8KB of Data RAM. A total of 8KB
of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can
be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
memories can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot
and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased.
programmable through the JTAG port, and 4KB of Program RAM and 8KB of Data RAM. A total of 8KB
of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can
be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
memories can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot
and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased.
A key application-specific feature of the 56F8322 is the inclusion of one Pulse Width Modulator (PWM)
module. This module incorporates three complementary, individually programmable PWM signal output
pairs and is also capable of supporting six independent PWM functions to enhance motor control
functionality. Complementary operation permits programmable dead time insertion, distortion correction
via current sensing by software, and separate top and bottom output polarity control. The up-counter value
module. This module incorporates three complementary, individually programmable PWM signal output
pairs and is also capable of supporting six independent PWM functions to enhance motor control
functionality. Complementary operation permits programmable dead time insertion, distortion correction
via current sensing by software, and separate top and bottom output polarity control. The up-counter value