Motorola CPCI-6020 ユーザーズマニュアル

The CPCI-6020 requires +5 V, +3.3 V, +1.8 V and +/-12 V (optional) input voltages. The 
processor core voltage and +2.5 V for the Harrier core are generated on board from the +5 V 
input by switching regulators. The processor core voltage regulator has a variable output which 
is set using feedback resistors. In addition to the Harrier core voltage, the +2.5 V supply will 
provide the processor, Harriers and L2 cache I/O voltage when the MPC7410 processor is 
used. Power resistors installed during assembly will select either +3.3 V or +2.5 V to supply the 
I/O voltage for the processor, Harriers and the L2 cache. +1.8 V is generated using an onboard 
regulator through +3.3 V.

A block diagram of the CPCI-6020 board reset logic is shown below. The board reset logic is 
implemented in a programmable logic device (PLD) in order to provide maximum flexibility of 
the circuit design.

There are several potential sources of reset on the CPCI-6020. They are:

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Power-on/under voltage reset

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Front panel reset switch

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CompactPCI PRST#

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Watchdog Timer reset via Harrier A WDT2

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CompactPCI FAL# signal

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Software generated hard reset via the Harrier RSTOUT bit

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Software generated hard reset via the Port 92 Register in the PBC

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CompactPCI Bus reset via the 21154 Bridge Control Register

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Processor RISCWatch JTAG emulator interface HRESET# signal (open collector)