Motorola CPCI-6020 ユーザーズマニュアル

Soft Reset

Functional Description

CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C)

4.10.5

Soft Reset

Software can assert the SRESET# pin of the processor by programming the P0 bit in the
Processor Init Register of the Harrier MPIC appropriately.

4.10.6

Front Panel Resources

The CPCI-6020 front panel provides access to recessed Abort and Reset push-button
switches, Board Fail, CPU Bus Activity and Hot Swap Status LEDs, an RJ-45 Ethernet
connector, an RJ-45 serial port connector, two USB connectors and the PMC front panel.

4.10.7

ABORT# and RESET# Switches

Two push-button switches provide ABORT# and RESET# inputs to the CPCI-6020. Both
switches are recessed to reduce the likelihood of accidental activation. The ABORT# signal is
connected to the Harrier Abort Switch (ABTSW_L) input and generates an MPIC internal
interrupt. The RESET# signal is connected to the Harrier Reset Switch (RSTSW_L) input which
will generate a Harrier Reset Out, which is ORed with the board reset logic. Each signal is
debounced in the Harrier ASIC.

Software Hard Reset
(Harrier RSTOUT,
PBC Port 92)

CompactPCI Reset
(21154 Bridge Control
Register)

Processor
RISCWatch JTAG
HRESET# Signal

(¸)

1. Available as a build option (not enabled in standard configuration).

Table 4-6 Reset Sources and Devices Affected (continued)

Device Affected

Processo
r

Harrier
ASIC

PCI
Devices

ISA
Devices

Local
CompactPCI
Bus