Intel 253668-032US ユーザーズマニュアル
Vol. 3 4-9
PAGING
corresponds to 1 TByte, linear addresses are limited to 32 bits; at most 4 GBytes of
linear-address space may be accessed at any given time.
32-bit paging uses a hierarchy of paging structures to produce a translation for a
linear address. CR3 is used to locate the first paging-structure, the page directory.
Table 4-3 illustrates how CR3 is used with 32-bit paging.
linear-address space may be accessed at any given time.
32-bit paging uses a hierarchy of paging structures to produce a translation for a
linear address. CR3 is used to locate the first paging-structure, the page directory.
Table 4-3 illustrates how CR3 is used with 32-bit paging.
Table 4-2. Paging Structures in the Different Paging Modes
Paging
Structure
Entry
Name
Paging Mode
Physical
Address of
Structure
Bits
Selecting
Entry
Page Mapping
PML4 table
PML4E
32-bit, PAE
N/A
IA-32e
CR3
47:39
N/A (PS must be 0)
Page-directory-
pointer table
PDPTE
32-bit
N/A
PAE
CR3
31:30
N/A (PS must be 0)
IA-32e
PML4E
38:30
Page directory
PDE
32-bit
CR3
31:22
4-MByte page if PS=1
1
PAE, IA-32e
PDPTE
29:21
2-MByte page if PS=1
Page table
PTE
32-bit
PDE
21:12
4-KByte page
PAE, IA-32e
20:12
4-KByte page
NOTES:
1. 32-bit paging ignores the PS flag in a PDE (and uses the entry to reference a page table) unless
CR4.PSE = 1. Not all processors allow CR4.PSE to be 1; see Section 4.1.4 for how to determine
whether 4-MByte pages are supported with 32-bit paging.
Table 4-3. Use of CR3 with 32-Bit Paging
Bit
Position(s)
Contents
2:0
Ignored
3 (PWT)
Page-level write-through; indirectly determines the memory type used to access
the page directory during linear-address translation (see Section 4.9)
4 (PCD)
Page-level cache disable; indirectly determines the memory type used to access
the page directory during linear-address translation (see Section 4.9)
11:5
Ignored