Intel 253668-032US ユーザーズマニュアル
4-10 Vol. 3
PAGING
32-bit paging may map linear addresses to either 4-KByte pages or 4-MByte pages.
Figure 4-2 illustrates the translation process when it uses a 4-KByte page; Figure 4-3
covers the case of a 4-MByte page. The following items describe the 32-bit paging
process in more detail as well has how the page size is determined:
Figure 4-2 illustrates the translation process when it uses a 4-KByte page; Figure 4-3
covers the case of a 4-MByte page. The following items describe the 32-bit paging
process in more detail as well has how the page size is determined:
•
A 4-KByte naturally aligned page directory is located at the physical address
specified in bits 31:12 of CR3 (see Table 4-3). A page directory comprises 1024
32-bit entries (PDEs). A PDE is selected using the physical address defined as
follows:
— Bits 39:32 are all 0.
— Bits 31:12 are from CR3.
— Bits 11:2 are bits 31:22 of the linear address.
— Bits 1:0 are 0.
specified in bits 31:12 of CR3 (see Table 4-3). A page directory comprises 1024
32-bit entries (PDEs). A PDE is selected using the physical address defined as
follows:
— Bits 39:32 are all 0.
— Bits 31:12 are from CR3.
— Bits 11:2 are bits 31:22 of the linear address.
— Bits 1:0 are 0.
31:12
Physical address of the 4-KByte aligned page directory used for linear-address
translation
63:32
Ignored (these bits exist only on processors supporting the Intel-64 architecture)
Figure 4-2. Linear-Address Translation to a 4-KByte Page using 32-Bit Paging
Table 4-3. Use of CR3 with 32-Bit Paging (Contd.)
Bit
Position(s)
Contents
0
Directory
Table
Offset
Page Directory
PDE with PS=0
CR3
Page Table
PTE
4-KByte Page
Physical Address
31
21
11
12
22
Linear Address
32
10
12
10
20
20