Intel E3815 FH8065301567411 데이터 시트

Intel

®

 Atom™ Processor E3800 Product Family

3802

Datasheet

The Enhanced SSP Control 0 registers contain twelve different bit fields that control 

various functions within the Enhanced SSP. All bits must be set to the preferred value 

before enabling the Enhanced SSP. Note that Writes to reserved bits must be zeroes, 

and Read values of these bits is undetermined.

Default: 00000000h

0–3h

4

00000000h

4–7h

4

00000000h

8–Bh

4

0000F004h

C–Fh

4

00000000h

10–13h

4

00000000h

28–2Bh

4

00000000h

2C–2Fh

4

00000000h

30–33h

4

00000000h

34–37h

4

00000000h

38–3Bh

4

00000000h

3C–3Fh

4

00000000h

40–43h

4

00000000h

44–47h

4

00000000h

48–4Bh

4

00000000h

400–403h

4

00000000h

404–407h

4

00000000h

408–40Bh

4

00000010h

40C–40Fh

4

00000000h

418–41Bh

4

00000000h

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:30, F:5] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MOD

AC

S

RS

VD

RS

VD

FRDC

TIM

RIM

NCS

EDS

S

SC

R

SSE

EC

S

FRF

DS

S