Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
3804
Datasheet
25.5.2
SSP Control Register 1 (SSCR1)—Offset 4h
The Enhanced SSP Control 1 registers contain bit fields that control various SSP
functions. Bits must be set to the preferred value before enabling the Enhanced SSP.
Note that Writes to reserved bits should be zeroes, and Read value of these bits are
undetermined.
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:30, F:5] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TT
E
LP
TT
E
EB
CE
I
SCF
R
EC
R
A
EC
R
B
SC
LKD
IR
SF
R
M
DIR
RWO
T
TRA
IL
TS
R
E
RSRE
TINTE
PINTE
RSVD
IFS
ST
RF
EF
W
R
RF
T
TF
T
MWDS
SP
H
SP
O
LBM
TIE
RIE
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
TXD Tristate Enable on Last Phase (TTELP):
•
•
0 = TXD line will be tristated on same clock edge as TXD is to be flopped
•
1 = TXD line will be tristated clock edge after TXD is to be flopped
30
0b
RW
TXD Tristate Enable (TTE):
•
•
0 = TXD line will not be tristated
•
1 = TXD line will be tristated when no transmitting data
29
0b
RW
Enable Bit Count Error Interrupt (EBCEI):
•
•
0 = Interrupt due to a bit count error is disabled
•
1 = Interrupt due to a bit count error is enabled
28
0b
RW
Slave Clock Free Running (SCFR):
•
•
0 = clock input to SSPSCLK is continuously running
•
1 = clock input to SSPSCLK is only active durring transfers
27
0b
RW
Enable Clock Request A (ECRA):
•
•
0 = clock request from other SSP is disabled
•
1 = clock request from other SSP is enabled
26
0b
RW
Enable Clock Request B (ECRB):
•
•
0 = clock request from other SSP is disabled
•
1 = clock request from other SSP is enabled
25
0b
RW
SSP Serial Bit Rate Clock (SSPSCLK) Direction (SCLKDIR):
•
•
0 = Master mode, SSP drives SSPSCLK
•
1 = Slave mode, SSP recieves SSPSCLK
24
0b
RW
SSP Frame (SSPSFRM) Direction (SFRMDIR):
•
•
0 = Master mode, SSP drives SSPSFRM
•
1 = Slave mode, SSP receives SSPSFRM
23
0b
RW
Receive With Out Transmit (RWOT):
•
•
0 = Transmit/Receive mode
•
1 = Receive without Transmit mode
22
0b
RW
Trailing Byte (TRAIL):
•
•
0 = Processor based, trailing bytes are handled by processor
•
1 = DMA based, trailing bytes are handled by DMA