Intel E3815 FH8065301567411 데이터 시트

Intel

®

 Atom™ Processor E3800 Product Family

4516

Datasheet

The LPC interface to the SoC is shown in 

. Note that the SoC implements all 

of the signals that are shown as optional, but peripherals are not required to do so.

The LPC controller does not implement bus mastering cycles or DMA.

The LPC controller is the subtractive agent of the Intel Legacy Block. All transactions 
not claimed elsewhere are sent to the LPC controller.

I/O

VLPC

LPC Multiplexed Command, Address, Data: Internal pull-ups are 
provided for these signals.
These signals are muxed and may be used by other functions.

O

VLPC

LPC Clock [0] Out: 33 MHz PCI-like clock driven to LPC peripherals.
These signals are muxed and may be used by other functions.

O or I

VLPC

LPC Clock [1] Out: 33 MHz PCI-like clock driven to LPC peripherals. 
Can be configured as an input to compensate for board routing delays 
through Soft Strap.
These signals are muxed and may be used by other functions.

I/OD

VLPC

LPC Clock Run: Input to determine the status of ILB_LPC_CLK and an 
open drain output used to request starting or speeding up 
ILB_LPC_CLK. This is a sustained tri-state signal used by the central 
resource to request permission to stop or slow ILB_LPC_CLK. The 
central resource is responsible for maintaining the signal in the 
asserted state when ILB_LPC_CLK is running and deasserts the signal 
to request permission to stop or slow ILB_LPC_CLK. An internal pull-up 
is provided for this signal.
This signal is muxed and may be used by other functions.

O

VLPC

LPC Frame: This signal indicates the start of an LPC cycle, or an abort.
This signal is muxed and may be used by other functions.

I/O

V1P8S

Serial Interrupt Request: This signal implements the serial interrupt 
protocol.
This signal is muxed and may be used by other functions.