Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
PCU – iLB – Low Pin Count (LPC) Bridge
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4517
NOTES:
1.
The General Purpose Input (GPI) must use a SMI capable GPIO: GPIO_S0_SC[7:0].
35.2.1
Memory Cycle Notes
For cycles below 16M, the LPC Controller will perform standard LPC memory cycles. For
cycles targeting firmware (BIOS/EFI code only), firmware memory cycles are used.
Only 8-bit transfers are performed. If a larger transfer appears, the LPC controller will
break it into multiple 8-bit transfers until the request is satisfied.
cycles targeting firmware (BIOS/EFI code only), firmware memory cycles are used.
Only 8-bit transfers are performed. If a larger transfer appears, the LPC controller will
break it into multiple 8-bit transfers until the request is satisfied.
If the cycle is not claimed by any peripheral (and subsequently aborted), the LPC
Controller will return a value of all 1’s to the CPU.
Controller will return a value of all 1’s to the CPU.
35.2.2
Trusted Platform Module (TPM) 1.2 Support
The LPC interface supports accessing Trusted Platform Module (TPM) 1.2 devices via
the LPC TPM START encoding. Memory addresses within the range FED40000h to
FED40FFFh will be accepted by the LPC Bridge and sent on LPC as TPM special cycles.
No additional checking of the memory cycle is performed.
the LPC TPM START encoding. Memory addresses within the range FED40000h to
FED40FFFh will be accepted by the LPC Bridge and sent on LPC as TPM special cycles.
No additional checking of the memory cycle is performed.
Note:
This is different to the FED00000h to FED4BFFFh range implemented on some other
Intel components since no Intel
Intel components since no Intel
®
Trusted Execution Technology (Intel
®
TXT)
transactions are supported.
35.2.3
FWH Cycle Notes
If the LPC controller receives any SYNC returned from the device other than short
(0101), long wait (0110), or ready (0000) when running a FWH cycle, indeterminate
results may occur. A FWH device is not allowed to assert an Error SYNC.
(0101), long wait (0110), or ready (0000) when running a FWH cycle, indeterminate
results may occur. A FWH device is not allowed to assert an Error SYNC.
BIOS/EFI boot from LPC is not supported when Secure Boot is enabled.
Figure 136.LPC Interface Diagram
S O C
L P C D e v ic e
L C L K
L R E S E T #
S E R IR Q (O p tio n a l)
L A D [3 :0 ]
L F R A M E #
L P C P D # (O p tio n a l)
P M C _ S U S _ S T A T #
L S M I# (O p tio n a l)
G P I
1
C L K R U N # (O p tio n a l)
IL B _ L P C _ C L K R U N #
IL B _ L P C _ S E R IR Q
IL B _ L P C _ C L K
P M C _ P L T R S T #
IL B _ L P C _ F R A M E #
IL B _ L P C _ A D [3 :0 ]