Intel E3815 FH8065301567411 데이터 시트
제품 코드
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
4558
Datasheet
37.6.4
TCW—Offset 43h
Timer Control Word Register. This register is programmed prior to any counter being
accessed to specify counter modes. Following reset, the control words for each register
are undefined and each counter output is 0. Each timer must be programmed to bring it
into a known state.
Access Method
Default: 00h
Bit
Range
Default &
Access
Description
7
0b
RO
CS:
Counter State (CS): When set, OUT of the counter is set. When cleared, OUT of the
counter is 0.
6
X
RO
CR:
Count Register: When cleared, indicates when the last count written to the Count
Register (CR) has been loaded into the counting element (CE) and is available for
reading. The time this happens depends on the counter mode.
5:4
X
RO
RWS:
Read/Write Selection: These reflect the read/write selection made through
bits[5:4] of the control register. The binary codes returned during the status read match
the codes used to program the counter read/write selection. 00 Counter Latch
Command 01 Read/Write Least Significant Byte (LSB) 10 Read/Write Most Significant
Byte (MSB) 11 Read/Write LSB then MSB
3:1
X
RO
MD:
Mode: Returns the counter mode programming. The binary code returned matches
the code used to program the counter mode, as listed under the bit function above. Bits
Mode Description 000 0 Out signal on end of count (=0) 001 1 Hardware retriggerable
one-shot x10 2 Rate generator (divide by n counter) x11 3 Square wave output 100 4
Software triggered strobe 101 5 Hardware triggered strobe
0
X
RO
CT:
Countdown Type: 0 for binary countdown or a 1 for binary coded decimal (BCD)
countdown.
Type:
I/O Register
(Size: 8 bits)
TCW:
7
4
0
0
0
0
0
0
0
0
0
CS
RWS
CMS
BCS
Bit
Range
Default &
Access
Description
7:6
X
WO
CS:
Counter Select (CS): The Counter Selection bits select the counter the control word
acts upon as shown below. The Read Back Command is selected when bits[7:6] are both
1 00 Counter 0 select 01 Counter 1 select 10 Counter 2 select 11 Read Back Command
5:4
X
WO
RWS:
Read/Write Select RWS): The counter programming is done through the counter
port (40h for counter 0, 41h for counter 1, and 42h for counter 2) 00 Counter Latch
Command 01 Read/Write Least Significant Byte (LSB) 10 Read/Write Most Significant
Byte (MSB) 11 Read/Write LSB then MSB
3:1
X
WO
CMS:
Counter Mode Selection (CMS): Selects one of six modes of operation for the
selected counter. 000 = Out signal on end of count (=0) 001 = Hardware retriggerable
one-shot x10 = Rate generator (divide by n counter) x11 = Square wave output 100 =
Software triggered strobe 101 = Hardware triggered strobe
0
X
WO
BCS:
Binary/BCD Countdown Select (BCS): 0 Binary countdown is used. The largest
possible binary count is 216 1 Binary coded decimal (BCD) count is used. The largest
possible BCD count is 104