Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

Freescale Semiconductor

183

In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. 
Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. 
Some modules can be programmed to be active in wait mode.

The MCU has these reset sources:

•

Power-on reset module (POR)

•

External reset pin (RST)

•

Computer operating properly (COP) module

•

Low-voltage inhibit (LVI) module

•

Illegal opcode

•

Illegal address

All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in monitor mode) and assert the 
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all 
modules to be returned to their reset states. 

An internal reset clears the SIM counter (see 

), but an external reset does not. Each of 

the resets sets a corresponding bit in the SIM reset status register (SRSR). See 

Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register 
(SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither 
the POR nor the LVI was the source of the reset. See 

 for details. 

 shows the relative 

timing.

PLL

OSC1

CGMXCLK

÷ 2

BUS CLOCK

GENERATORS

SIM COUNTER

PTC2

MONITOR MODE

CLOCK

SELECT

CIRCUIT

CGMVCLK

BCS

÷ 2

A

B S*

CGMOUT

*When S = 1,

CGMOUT = B

USER MODE