Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador
System Integration Module (SIM)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
184
Freescale Semiconductor
Figure 14-3. External Reset Timing
14.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of
external peripherals. The internal reset signal (IRST) continues to be asserted for an additional 32 cycles
(see
external peripherals. The internal reset signal (IRST) continues to be asserted for an additional 32 cycles
(see
). An internal reset can be caused by an illegal address, illegal opcode, COP timeout,
LVI, or POR. (See
Figure 14-4. Sources of Internal Reset
NOTE
For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST, as shown in
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST, as shown in
.
Figure 14-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
built around the MCU.
Table 14-2. PIN Bit Set Timing
Reset Type
Number of Cycles Required to Set PIN
POR/LVI
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
RST
IAB
PC
VECT H
VECT L
CGMOUT
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
IRST
RST
RST PULLED LOW BY MCU
IAB
32 CYCLES
32 CYCLES
VECTOR HIGH
CGMXCLK