Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

Freescale Semiconductor

187

Normal, sequential program execution can be changed in three different ways:

1.

Interrupts:

a.

Maskable hardware CPU interrupts

b.

Non-maskable software interrupt instruction (SWI)

2.

Reset

3.

Break interrupts

At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the 
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the return-from-interrupt 
(RTI) instruction recovers the CPU register contents from the stack so that normal processing can 
resume. 

 shows interrupt entry timing. 

 shows interrupt recovery timing.

. 

Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The 
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is 
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched 
interrupt is serviced (or the I bit is cleared). See 

MODULE

IDB

R/W

INTERRUPT

DUMMY

SP

SP – 1

SP – 2

SP – 3

SP – 4

VECT H

VECT L

IAB

DUMMY

PC – 1[7:0] PC – 1[15:8]

X

A

CCR

V DATA H

V DATA L

OPCODE

I BIT

START

ADDR