Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador
System Integration Module (SIM)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
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Freescale Semiconductor
signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external
noise. During a break state, V
noise. During a break state, V
HI
on the RST pin disables the COP module.
14.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
bit in the SIM reset status register (SRSR) and causes a reset.
Because the MC68HC908MR32 has stop mode disabled, execution of the STOP instruction will cause
an illegal opcode reset.
an illegal opcode reset.
14.3.2.4 Illegal Address Reset
An opcode fetch from addresses other than FLASH or RAM addresses generates an illegal address reset
(unimplemented locations within memory map). The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from
an unmapped address does not generate a reset.
(unimplemented locations within memory map). The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from
an unmapped address does not generate a reset.
14.3.2.5 Forced Monitor Mode Entry Reset (MENRST)
The MENRST module monitors the reset vector fetches and will assert an internal reset if it detects that
the reset vectors are erased ($FF). When the MCU comes out of reset, it is forced into monitor mode.
the reset vectors are erased ($FF). When the MCU comes out of reset, it is forced into monitor mode.
14.3.2.6 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit (LVI) module asserts its output to the SIM when the V
DD
voltage falls to the V
LVRX
voltage and remains at or below that level for at least nine consecutive CPU cycles (see
). The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin
(RST) is held low while the SIM counter counts out 4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles
later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls
down the RST pin for all internal reset sources.
later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls
down the RST pin for all internal reset sources.
14.4 SIM Counter
The SIM counter is used by the power-on reset (POR) module to allow the oscillator time to stabilize
before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the
computer operating properly (COP) module. The SIM counter overflow supplies the clock for the COP
module. The SIM counter is 13 bits long and is clocked by the falling edge of CGMXCLK.
before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the
computer operating properly (COP) module. The SIM counter overflow supplies the clock for the COP
module. The SIM counter is 13 bits long and is clocked by the falling edge of CGMXCLK.
14.4.1 SIM Counter During Power-On Reset
The power-on reset (POR) module detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation (CGM) module to
drive the bus clock state machine.
asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation (CGM) module to
drive the bus clock state machine.
14.4.2 SIM Counter and Reset States
External reset has no effect on the SIM counter. The SIM counter is free-running after all reset states. For
counter control and internal reset recovery sequences, see
counter control and internal reset recovery sequences, see