Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

Freescale Semiconductor

225

The TIMA remains active after the execution of a WAIT instruction. In wait mode, the TIMA registers are 
not accessible by the CPU. Any enabled CPU interrupt request from the TIMA can bring the MCU out of 
wait mode.

If TIMA functions are not required during wait mode, reduce power consumption by stopping the TIMA 
before executing the WAIT instruction.

Port E shares five of its pins with the TIMA: 

•

PTE3/TCLKA is an external clock input to the TIMA prescaler. 

•

The four TIMA channel I/O pins are PTE4/TCH0A, PTE5/TCH1A, PTE6/TCH2A, and 
PTE7/TCH3A.

PTE3/TCLKA is an external clock input that can be the clock source for the TIMA counter instead of the 
prescaled internal bus clock. Select the PTE3/TCLKA

 

input by writing logic 1s to the three prescaler select 

bits, PS[2:0]. See 

The maximum TCLK frequency is the least: 4 MHz or bus frequency 

÷ 2.

PTE3/TCLKA is available as a general-purpose I/O pin when not used as the TIMA clock input. When the 
PTE3/TCLKA pin is the TIMA clock input, it is an input regardless of the state of the DDRE3 bit in data 
direction register E.

Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. 
PTE2/TCH0

 

and

 

PTE4/TCH2 can be configured as buffered output compare or buffered PWM pins.

These input/output (I/O) registers control and monitor TIMA operation:

•

TIMA status and control register (TASC)

•

TIMA control registers (TACNTH–TACNTL)

•

TIMA counter modulo registers (TAMODH–TAMODL)

•

TIMA channel status and control registers (TASC0, TASC1, TASC2, and TASC3)

•

TIMA channel registers (TACH0H–TACH0L, TACH1H–TACH1L, TACH2H–TACH2L, and 
TACH3H–TACH3L)

The TIMA status and control register:

•

Enables TIMA overflow interrupts

•

Flags TIMA overflows

•

Stops the TIMA counter

•

Resets the TIMA counter

•

Prescales the TIMA counter clock