Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

Freescale Semiconductor

251

This section describes the break module, the monitor read-only memory (MON), and the monitor mode 
entry methods.

The break module (BRK) can generate a break interrupt that stops normal program flow at a defined 
address to enter a background program. Features include:

•

Accessible input/output (I/O) registers during the break interrupt

•

Central processor unit (CPU) generated break interrupts

•

Software-generated break interrupts

•

Computer operating properly (COP) disabling during break interrupts

When the internal address bus matches the value written in the break address registers, the break module 
issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software 
interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors 
to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).

These events can cause a break interrupt to occur:

•

A CPU-generated address (the address in the program counter) matches the contents of the break 
address registers.

•

Software writes a logic 1 to the BRKA bit in the break status and control register.

When a CPU-generated address matches the contents of the break address registers, the break interrupt 
begins after the CPU completes its current instruction. A return-from-interrupt instruction (RTI) in the 
break routine ends the break interrupt and returns the microcontroller unit (MCU) to normal operation. 

 shows the structure of the break module.

The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during 
the break state.