Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador
I/O Registers
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
55
In 8-bit mode, this 8-bit result register holds the eight MSBs of the 10-bit result. This register is updated
each time an ADC conversion completes. In 8-bit mode, this register contains no interlocking with ADRH.
each time an ADC conversion completes. In 8-bit mode, this register contains no interlocking with ADRH.
3.7.4 ADC Clock Register
This register selects the clock frequency for the ADC, selecting between modes of operation.
ADIV2:ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock.
the internal ADC clock.
shows the available clock configurations.
Address:
$0042
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
R
R
R
R
R
R
R
R
Reset:
Unaffected by reset
R
= Reserved
Figure 3-8. ADC Data Register Low (ADRL) Right Justified Mode
Address:
$0042
Bit 7
6
5
4
3
2
1
Bit 0
Read:
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
Write:
R
R
R
R
R
R
R
R
Reset:
Unaffected by reset
R
= Reserved
Figure 3-9. ADC Data Register Low (ADRL) 8-Bit Mode
Address:
$0043
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ADIV2
ADIV1
ADIV0
ADICLK
MODE1
MODE0
0
0
Write:
R
Reset:
0
0
0
0
0
1
0
0
R
= Reserved
Figure 3-10. ADC Clock Register (ADCLK)
Table 3-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
0
0
0
ADC input clock
÷ 1
0
0
1
ADC input clock
÷ 2
0
1
0
ADC input clock
÷ 4
0
1
1
ADC input clock
÷ 8
1
X
X
ADC input clock
÷ 16
X = don’t care