Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

Freescale Semiconductor

57

This section describes the clock generator module (CGM, version A). The CGM generates the crystal 
clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the 
base clock signal, CGMOUT, from which the system integration module (SIM) derives the system clocks. 

CGMOUT is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, 
CGMVCLK, divided by two. The PLL is a frequency generator designed for use with crystals or ceramic 
resonators. The PLL can generate an 8-MHz bus frequency without using a 32-MHz external clock.

Features of the CGM include:

•

PLL with output frequency in integer multiples of the crystal reference

•

Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation

•

Automatic bandwidth control mode for low-jitter operation

•

Automatic frequency lock detector

•

Central processor unit (CPU) interrupt on entry or exit from locked condition

The CGM consists of three major submodules:

1.

Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency 
clock, CGMXCLK.

2.

Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock, 
CGMVCLK.

3.

Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by 
two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives 
the system clocks from CGMOUT.

 shows the structure of the CGM.