Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

60

Freescale Semiconductor

The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final 
reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final 
reference frequency, f

RDV

. The circuit determines the mode of the PLL and the lock condition based on 

this comparison.

The PLL filter is manually or automatically configurable into one of two operating modes:

1.

Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the 
VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the 
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in 
the PLL bandwidth control register. See 

.

2.

Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the 
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL 
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected 
as the base clock source. See 

. The PLL is automatically in 

tracking mode when not in acquisition mode or when the ACQ bit is set. 

The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.

In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between 
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the 
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. See 

. If PLL interrupts are enabled, the software can wait for a PLL interrupt 

request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit 
continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is set, 
the VCO clock is safe to use as the source for the base clock. See 

. If 

the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a 
severe noise hit and the software must take appropriate action, depending on the application. See 

 for information and precautions on using interrupts. 

These conditions apply when the PLL is in automatic bandwidth control mode:

•

The  ACQ bit (see 

) is a read-only indicator of the mode of the 

filter. For more information, see 

.

•

The  ACQ bit is set when the VCO frequency is within a certain tolerance, 

∆

TRK

, and is cleared when 

the VCO frequency is out of a certain tolerance, 

∆

UNT

. For more information, see 

•

The LOCK bit is a read-only indicator of the locked state of the PLL.

•

The LOCK bit is set when the VCO frequency is within a certain tolerance, 

∆

Lock

, and is cleared 

when the VCO frequency is out of a certain tolerance, 

∆

UNL

. For more information, see 

•

CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling 
the LOCK bit. For more information, see