Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

62

Freescale Semiconductor

5.

Calculate the bus frequency, f

BUS

, and compare f

BUS

 with f

BUSDES

.

6.

If the calculated f

BUS

 is not within the tolerance limits of the application, select another f

BUSDES

 or 

another f

RCLK

.

7.

Using the value 4.9152 MHz for f

NOM

, calculate the VCO linear range multiplier, L. The linear range 

multiplier controls the frequency range of the PLL.

8.

Calculate the VCO center-of-range frequency, f

VRS

. The center-or-range frequency is the midpoint 

between the minimum and maximum frequencies attainable by the PLL.

f

VRS

 = L x f

NOM

Example: f

VRS

 = 7 x 4.9152 MHz = 34.4 MHz

For proper operation,

9.

Program the PLL registers accordingly:

a.

In the upper four bits of the PLL programming register (PPG), program the binary equivalent 
of N.

b.

In the lower four bits of the PLL programming register (PPG), program the binary equivalent 
of L.

The programming method described in 

 does not account for possible 

exceptions. A value of 0 for N or L is meaningless when used in the equations given. To account for these 
exceptions:

•

A 0 value for N is interpreted exactly the same as a value of 1. 

•

A 0 value for L disables the PLL and prevents its selection as the source for the base clock. See 

.

This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the 
source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits 
up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other. 
During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by 

f

BUS

 =

f

VCLK

4

Example: N =

32 MHz

4 MHz

= 8 MHz

Example: L =

32 MHz

4.9152 MHz

= 7 MHz

L = round

f

VCLK

f

NOM

(

)

f

VRS

 – f

VCLK

 | 

≤

f

NOM

2