Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

Freescale Semiconductor

63

two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock 
frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).

The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock 
cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if 
the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or 
deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the 
factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the 
PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base 
clock.

In its typical configuration, the CGM requires seven external components. Five of these are for the crystal 
oscillator and two are for the PLL.

The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in 

 shows only the logical representation of the internal components and may not represent actual 

circuitry. 

The oscillator configuration uses five components:

1.

Crystal, X

1

2.

Fixed capacitor, C

1

3.

Tuning capacitor, C

2

 (can also be a fixed capacitor)

4.

Feedback resistor, R

B

5.

Series resistor, R

S

 (optional)

The series resistor (R

S

) is included in the diagram to follow strict Pierce oscillator guidelines and may not 

be required for all ranges of operation, especially with high-frequency crystals. Refer to the crystal 
manufacturer’s data for more information. 

C1

C2

C

F

SIMOSCEN

CGMXCLK

R

B

X1

R

S

*

C

BYP

OSC1

OSC2

V

SS

CGMXFC

V

DDA

V

DD

*RS can be 0 (shorted) when used with

higher frequency crystals. Refer to
manufacturer’s data.