Freescale Semiconductor MC68HC908MR32 Manual Do Utilizador

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Freescale Semiconductor

The COP counter is a free-running, 6-bit counter preceded by the 13-bit system integration module (SIM) 
counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 
2

18

–2

4

 CGMXCLK cycles. With a 4.9152-MHz crystal, the COP timeout period is 53.3 ms. Writing any 

value to location $FFFF before overflow occurs clears the COP counter and prevents reset.

A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the SIM reset status 
register (SRSR). See 

This section describes the signals shown in 

.

CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.

Writing any value to the COP control register (COPCTL) (see 

) clears the COP 

counter and clears bits 12–4 of the SIM counter. Reading the COP control register returns the reset 
vector.

The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 CGMXCLK cycles after 
power-up.

An internal reset clears the SIM counter and the COP counter.

A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears 
the SIM counter.

$FFFF

COP Control Register

(COPCTL)

Read:

Low byte of reset vector

Write:

Clear COP counter

Reset:

Unaffected by reset