Intel D525 AU80610006225AA Manual Do Utilizador
Códigos do produto
AU80610006225AA
Datasheet
11
Introduction
1.5
Clocking
•
Differential Core clock of 166MHz and 200 MHz (BCLKP/BCLKN). Core clock and
Host clock need to match one another. If Core clock is 166 MHz, Host clock needs to
be 166 MHz.
Host clock need to match one another. If Core clock is 166 MHz, Host clock needs to
be 166 MHz.
•
Differential Host clock of 166 MHz and 200 MHz (HPL_CLKINP/HPL_CLKINN).
•
Memory clocks
— When running DDR2-667, memory clocks are generated from internal Host PLL.
— When running DDR2-800, memory clocks are generated from the Memory PLL
•
The differential DMI clock of 100 MHz (EXP_CLKINP/EXP_CLKINN) generates the
DMI core clock of 250 MHz.
DMI core clock of 250 MHz.
•
Display timings are generated from display PLLs that use a 96 MHz differential SSC
and non-SSC, and 100 MHz differential clock with SSC as reference.
and non-SSC, and 100 MHz differential clock with SSC as reference.
•
Host, Memory, DMI, Display PLLs and all associated internal clocks are disabled
until PWROK is asserted.
until PWROK is asserted.
1.6
Power Management
•
PC99 suspend to DRAM support (“STR”, mapped to ACPI state S3)
•
SMRAM space remapping to A0000h (128 kB)
•
Support extended SMRAM space above 256 MB, additional 1MB TSEG from the
base of graphics stolen memory (BSM) when enabled, and cacheable (cacheability
controlled by CPU).
base of graphics stolen memory (BSM) when enabled, and cacheable (cacheability
controlled by CPU).
•
ACPI Rev 1.0b compatible power management
•
Support CPU states: C0 and C1
•
Support System states: S0, S3, S4 and S5
•
Support CPU Thermal Management 1 (TM1)
1.6.1
Terminology
Term
Description
BGA
Ball Grid Array
BLT
Block Level Transfer
CRT
Cathode Ray Tube
DDR2
Second generation Double Data Rate SDRAM memory technology
DMA
Direct Memory Access
DMI
Direct Media Interface
DTS
Digital Thermal Sensor
ECC
Error Correction Code