Intel D525 AU80610006225AA User Manual

Datasheet

11

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Differential Core clock of 166MHz and 200 MHz (BCLKP/BCLKN). Core clock and 
Host clock need to match one another. If Core clock is 166 MHz, Host clock needs to 
be 166 MHz.

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Differential Host clock of 166 MHz and 200 MHz (HPL_CLKINP/HPL_CLKINN).

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Memory clocks

— When running DDR2-667, memory clocks are generated from internal Host PLL.

— When running DDR2-800, memory clocks are generated from the Memory PLL

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The differential DMI clock of 100 MHz (EXP_CLKINP/EXP_CLKINN) generates the 
DMI core clock of 250 MHz.

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Display timings are generated from display PLLs that use a 96 MHz differential SSC 
and non-SSC, and 100 MHz differential clock with SSC as reference.

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Host, Memory, DMI, Display PLLs and all associated internal clocks are disabled 
until PWROK is asserted.

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PC99 suspend to DRAM support (“STR”, mapped to ACPI state S3)

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SMRAM space remapping to A0000h (128 kB)

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Support extended SMRAM space above 256 MB, additional 1MB TSEG from the 
base of graphics stolen memory (BSM) when enabled, and cacheable (cacheability 
controlled by CPU).

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ACPI Rev 1.0b compatible power management

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Support CPU states: C0 and C1

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Support System states: S0, S3, S4 and S5

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Support CPU Thermal Management 1 (TM1)

BGA

Ball Grid Array

BLT

Block Level Transfer

CRT

Cathode Ray Tube

DDR2

Second generation Double Data Rate SDRAM memory technology

DMA

Direct Memory Access

DMI

Direct Media Interface

DTS

Digital Thermal Sensor

ECC

Error Correction Code