Техническая Спецификация для Intel D2500 DF8064101055400
Модели
DF8064101055400
10
Datasheet - Volume 1 of 2
1.2
System Memory Features
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One channel of DDR3
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memory (consists of 64 data lines):
— Maximum of two SODIMMs per channel for D2000 series and N2800 Processor
— Maximum of two SODIMMs per channel for D2000 series and N2800 Processor
performance, containing single or double-sided SODIMM
— Maximum of one SODIMMs per channel for N2600 series Processor only,
containing single or double-sided SODIMM.
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Memory DDR3 data transfer rates of 800 MT/s (6.4 GB/s) and 1066 MT/s
(8.5 GB/s)
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Only non-ECC SODIMMs are supported
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Refreshed SKU of Next Generation Intel® Atom™ Processor based Mobile Platform
Processors support DDR3/DDR3L.
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Support Small Outline DIMMs Raw Cards RC-A (2Rx16), RC-B(1Rx8), RC-C (1Rx16)
and RC-F (2Rx8) for DDR3. Support Small Outline DIMMs Raw Cards RC-B (1Rx8)
and RC-F (2Rx8) for DDR3L.
— Does not support RC-D (2Rx16 dual die), and RC-E(2Rx16)
— No mixed Raw Card support.
— Does not support RC-D (2Rx16 dual die), and RC-E(2Rx16)
— No mixed Raw Card support.
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Support unbuffered SODIMMs
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Supports Memory Down Design with Raw Card Type B only
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I/O Voltage of 1.5 V for DDR3. I/O Voltage of 1.35 V for DDR3L.
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Max memory size by sku: N2600 series 2 GB; N2800, D2500 & D2700 series 4 GB
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Supports total memory size of 1 GB, 2 GB and 4 GB max
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Supports Max densities 1 Gbit, 2 Gbit for both x8 and x16 for DDR3
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DRAM Chip Data Width: x8 and x16
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Banks / DRAM Chip: 8
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Support up to 32 simultaneous open pages per channel (assuming 4 ranks of
8 devices)
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Support Partial Writes to memory using Data Mask signals (DM)
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Enhances Address Mapping
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Support DIMM page size of 1 KB and 2 KB
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Support data burst length of 8 and Burst Chopped of 4 for all memory
configurations
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Support memory thermal management scheme to selectively manage reads and/or
writes. Memory thermal management can be triggered by either on-die thermal
sensor, or by preset limits. Management limits are determined by weighted sum of
various commands that are scheduled on the memory interface.