Aethra d2061 用户手册
USER’S MANUAL
ADSL TESTER D2061
the previous super frame.
LOF: Loss of Frame
Near-End: indicates that the sum of the number of tones with a mismatch between
the expected and measured bit pattern exceeds the threshold in 2 consecutive
synchronization symbols.
the expected and measured bit pattern exceeds the threshold in 2 consecutive
synchronization symbols.
If the threshold equals the number of active tones (which is the default), an LOF
indicates that half of the active tones carry the wrong information. Far-End: indicates
that a near-end loss of frame was detected in the previous super frame.
indicates that half of the active tones carry the wrong information. Far-End: indicates
that a near-end loss of frame was detected in the previous super frame.
LOP: Loss of Power
Near-End: occurs when the ATU-R power level drops below the nominal power level
needed for proper operation of the ATU-R.
needed for proper operation of the ATU-R.
Far-End: indicates that a LOP indicator has been received.
LCD INTER: Loss of Cell Delineation, interleaved latency path.
LCD FAST: Loss of Cell Delineation, fast latency path.
LOM: Loss of Margin.
Near-End: occurs when the measured signal-to-noise ratio (neared) is below the
required signal-to-noise ratio, as provided by the operator.
required signal-to-noise ratio, as provided by the operator.
Far-End: occurs when the downstream signal-to-noise margin is below the minimum
required downstream signal-to-noise margin, as required by the operator.
required downstream signal-to-noise margin, as required by the operator.
6.2.4. ADSL Errors Status
The Errors Status screen provides a current status of any error conditions.
The left column displays results for the upstream signal (received by the ATU-C); the
right column shows results for the downstream signal (received by the ATU-R). Each
result is shown for the interleaved and fast latency paths. A circuit will be using one
right column shows results for the downstream signal (received by the ATU-R). Each
result is shown for the interleaved and fast latency paths. A circuit will be using one
CHAPTER 6 - SMART STATUS
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