Toshiba Xeon 2.8GHz UPG3843W 用户手册
产品代码
UPG3843W
Intel® Xeon™ Processor with 512 KB L2 Cache
114
Datasheet
Table 56. Thermal Sensor SMBus Addressing
NOTES:
1. Upper address bits are decoded in conjunction with the select pins.
2. A tri-state or “Z” state on this pin is achieved by leaving this pin unconnected.
Note:
System management software must be aware of the processor dependent addresses for the thermal
sensor.
sensor.
Table 57. Memory Device SMBus Addressing
NOTES:
1. . This addressing scheme will support up to 8 processors on a single SMBus.
Address (Hex)
Upper
Address
1
Device Select
8-bit Address Word on Serial Bus
SM_TS_A1
SM_TS_A0
b[7:0]
3Xh
0011
0
Z
2
1
0
0
0
0011000Xb
0011001Xb
0011010Xb
5Xh
0101
0
Z
2
1
Z
2
Z
2
Z
2
0101001Xb
0101010Xb
0101011Xb
9Xh
1001
0
Z
2
1
1
1
1
1001100Xb
1001101Xb
1001110Xb
Address
(Hex)
Upper
Address
1
Device Select
R/W
bits 7-4
SM_EP_A2
bit 3
SM_EP_A1
bit 2
SM_EP_A0
bit 1
bit 0
A0h/A1h
1010
0
0
0
X
A2h/A3h
1010
0
0
1
X
A4h/A5h
1010
0
1
0
X
A6h/A7h
1010
0
1
1
X
A8h/A9h
1010
1
0
0
X
AAh/ABh
1010
1
0
1
X
ACh/ADh
1010
1
1
0
X
AEh/AFh
1010
1
1
1
X