Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD 数据表
产品代码
ATSAM4S-WPIR-RD
705
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
Figure 34-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 34-12. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
34.8.6.2 10-bit Slave Addressing
For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave
address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8]
and IADR[23:16] can be used the same as in 7-bit Slave Addressing.
Example:
Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
1. Program IADRSZ = 1,
2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address)
3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address)
below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal
addresses to access the device.
Figure 34-13. Internal Address Usage
34.8.7 Using the Peripheral DMA Controller (PDC)
The use of the PDC significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequences:
To assure correct implementation, respect the following programming sequences:
34.8.7.1 Data Transmit with the PDC
1. Initialize the transmit PDC (memory pointers, transfer size - 1).
2. Configure the master (DADR, CKDIV, etc.) or slave mode.
S
DADR
W
A
IADR(23:16)
A
IADR(15:8)
A
IADR(7:0)
A
DATA
A
P
S
DADR
W
A
IADR(15:8)
A
IADR(7:0)
A
P
DATA
A
A
IADR(7:0)
A
P
DATA
A
S
DADR
W
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
TWD
TWD
S
DADR
W
A
IADR(23:16)
A
IADR(15:8)
A
IADR(7:0)
A
S
DADR
W
A
IADR(15:8)
A
IADR(7:0)
A
A
IADR(7:0)
A
S
DADR
W
DATA
NA
P
Sr
DADR
R
A
Sr
DADR
R
A
DATA
NA
P
Sr
DADR
R
A
DATA
NA
P
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
S
T
A
R
T
T
A
R
T
M
S
B
B
Device
Address
0
L
S
B
B
R
/
W
A
C
K
C
K
M
S
B
B
W
R
I
T
E
E
A
C
K
C
K
A
C
K
C
K
L
S
B
B
A
C
K
C
K
FIRST
WORD ADDRESS
SECOND
WORD ADDRESS
DATA
S
T
T
O
P