数据表 (ATSAM4S-WPIR-RD)目录Description1Features21. Configuration Summary42. Block Diagram63. Signal Description134. Package and Pinout174.1 100-lead Packages and Pinouts174.1.1 100-lead LQFP Package Outline174.1.2 100-ball TFBGA Package Outline174.1.3 100-ball VFBGA Package Outline184.1.4 100-lead LQFP Pinout194.1.5 100-ball TFBGA Pinout204.1.6 100-ball VFBGA Pinout214.2 64-lead Packages and Pinouts224.2.1 64-lead LQFP Package Outline224.2.2 64-lead QFN Package Outline224.2.3 64-ball WLCSP Package Outline234.2.4 64-lead LQFP and QFN Pinout234.2.5 64-ball WLCSP Pinout244.3 48-lead Packages and Pinouts254.3.1 48-lead LQFP Package Outline254.3.2 48-lead QFN Package Outline254.3.3 48-lead LQFP and QFN Pinout265. Power Considerations275.1 Power Supplies275.2 Voltage Regulator275.3 Typical Powering Schematics285.4 Active Mode295.5 Low-power Modes295.5.1 Backup Mode305.5.2 Wait Mode305.5.3 Sleep Mode315.5.4 Low-power Mode Summary Table315.6 Wake-up Sources335.7 Fast Start-up336. Input/Output Lines346.1 General Purpose I/O Lines346.2 System I/O Lines346.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins356.3 Test Pin356.4 NRST Pin366.5 ERASE Pin366.6 Anti-tamper Pins/Low-power Tamper Detection367. Product Mapping378. Memories388.1 Embedded Memories388.1.1 Internal SRAM388.1.2 Internal ROM388.1.3 Embedded Flash388.1.3.1 Flash Overview388.1.3.2 Enhanced Embedded Flash Controller418.1.3.3 Flash Speed418.1.3.4 Lock Regions428.1.3.5 Security Bit428.1.3.6 Calibration Bits428.1.3.7 Unique Identifier438.1.3.8 User Signature438.1.3.9 Fast Flash Programming Interface438.1.3.10 SAM-BA Boot438.1.3.11 GPNVM Bits438.1.4 Boot Strategies448.2 External Memories458.2.1 Static Memory Controller459. Real Time Event Management469.1 Embedded Characteristics469.2 Real Time Event Mapping List4710. System Controller4810.1 System Controller and Peripheral Mapping4810.2 Power-on-Reset, Brownout and Supply Monitor4810.2.1 Power-on-Reset4810.2.2 Brownout Detector on VDDCORE4810.2.3 Supply Monitor on VDDIO4811. Peripherals4911.1 Peripheral Identifiers4911.2 Peripheral Signal Multiplexing on I/O Lines5011.2.1 PIO Controller A Multiplexing5111.2.2 PIO Controller B Multiplexing5211.2.3 PIO Controller C Multiplexing5312. ARM Cortex-M4 Processor5412.1 Description5412.1.1 System Level Interface5412.1.2 Integrated Configurable Debug5412.2 Embedded Characteristics5512.3 Block Diagram5512.4 Cortex-M4 Models5612.4.1 Programmers Model5612.4.1.1 Processor Modes and Privilege Levels for Software Execution5612.4.1.2 Stacks5612.4.1.3 Core Registers5712.4.1.4 General-purpose Registers5812.4.1.5 Stack Pointer5812.4.1.6 Link Register5812.4.1.7 Program Counter5812.4.1.8 Program Status Register5912.4.1.9 Application Program Status Register6012.4.1.10 Interrupt Program Status Register6112.4.1.11 Execution Program Status Register6212.4.1.12 Exception Mask Registers6312.4.1.13 Priority Mask Register6412.4.1.14 Fault Mask Register6512.4.1.15 Base Priority Mask Register6612.4.1.16 Control Register6712.4.1.17 Exceptions and Interrupts6812.4.1.18 Data Types6812.4.1.19 Cortex Microcontroller Software Interface Standard (CMSIS)6812.4.2 Memory Model6912.4.2.1 Memory Regions, Types and Attributes7012.4.2.2 Memory System Ordering of Memory Accesses7012.4.2.3 Behavior of Memory Accesses7112.4.2.4 Software Ordering of Memory Accesses7212.4.2.5 Bit-banding7212.4.2.6 Memory Endianness7412.4.2.7 Synchronization Primitives7512.4.2.8 Programming Hints for the Synchronization Primitives7612.4.3 Exception Model7612.4.3.1 Exception States7612.4.3.2 Exception Types7712.4.3.3 Exception Handlers7912.4.3.4 Vector Table7912.4.3.5 Exception Priorities8012.4.3.6 Interrupt Priority Grouping8012.4.3.7 Exception Entry and Return8012.4.3.8 Fault Handling8412.5 Power Management8612.5.1 Entering Sleep Mode8612.5.1.1 Wait for Interrupt8612.5.1.2 Wait for Event8612.5.1.3 Sleep-on-exit8612.5.2 Wakeup from Sleep Mode8612.5.2.1 Wakeup from WFI or Sleep-on-exit8612.5.2.2 Wakeup from WFE8612.5.2.3 External Event Input8712.5.3 Power Management Programming Hints8712.6 Cortex-M4 Instruction Set8812.6.1 Instruction Set Summary8812.6.2 CMSIS Functions9412.6.3 Instruction Descriptions9512.6.3.1 Operands9512.6.3.2 Restrictions when Using PC or SP9512.6.3.3 Flexible Second Operand9612.6.3.4 Shift Operations9712.6.3.5 Address Alignment9912.6.3.6 PC-relative Expressions9912.6.3.7 Conditional Execution9912.6.3.8 Instruction Width Selection10112.6.4 Memory Access Instructions10312.6.4.1 ADR10412.6.4.2 LDR and STR, Immediate Offset10512.6.4.3 LDR and STR, Register Offset10712.6.4.4 LDR and STR, Unprivileged10912.6.4.5 LDR, PC-relative11012.6.4.6 LDM and STM11112.6.4.7 PUSH and POP11312.6.4.8 LDREX and STREX11412.6.4.9 CLREX11512.6.5 General Data Processing Instructions11612.6.5.1 ADD, ADC, SUB, SBC, and RSB11812.6.5.2 AND, ORR, EOR, BIC, and ORN11912.6.5.3 ASR, LSL, LSR, ROR, and RRX12112.6.5.4 CLZ12212.6.5.5 CMP and CMN12312.6.5.6 MOV and MVN12412.6.5.7 MOVT12512.6.5.8 REV, REV16, REVSH, and RBIT12512.6.5.9 SADD16 and SADD812712.6.5.10 SHADD16 and SHADD812812.6.5.11 SHASX and SHSAX12912.6.5.12 SHSUB16 and SHSUB813012.6.5.13 SSUB16 and SSUB813112.6.5.14 SASX and SSAX13212.6.5.15 TST and TEQ13212.6.5.16 UADD16 and UADD813312.6.5.17 UASX and USAX13512.6.5.18 UHADD16 and UHADD813512.6.5.19 UHASX and UHSAX13612.6.5.20 UHSUB16 and UHSUB813812.6.5.21 SEL13812.6.5.22 USAD814012.6.5.23 USADA814112.6.5.24 USUB16 and USUB814212.6.6 Multiply and Divide Instructions14312.6.6.1 MUL, MLA, and MLS14412.6.6.2 UMULL, UMAAL, UMLAL14412.6.6.3 SMLA and SMLAW14512.6.6.4 SMLAD14712.6.6.5 SMLAL and SMLALD14812.6.6.6 SMLSD and SMLSLD15112.6.6.7 SMMLA and SMMLS15312.6.6.8 SMMUL15412.6.6.9 SMUAD and SMUSD15412.6.6.10 SMUL and SMULW15612.6.6.11 UMULL, UMLAL, SMULL, and SMLAL15812.6.6.12 SDIV and UDIV15912.6.7 Saturating Instructions16012.6.7.1 SSAT and USAT16112.6.7.2 SSAT16 and USAT1616212.6.7.3 QADD and QSUB16212.6.7.4 QASX and QSAX16412.6.7.5 QDADD and QDSUB16612.6.7.6 UQASX and UQSAX16712.6.7.7 UQADD and UQSUB16812.6.8 Packing and Unpacking Instructions17012.6.8.1 PKHBT and PKHTB17112.6.8.2 SXT and UXT17212.6.8.3 SXTA and UXTA17312.6.9 Bitfield Instructions17512.6.9.1 BFC and BFI17612.6.9.2 SBFX and UBFX17712.6.9.3 SXT and UXT17812.6.10 Branch and Control Instructions17912.6.10.1 B, BL, BX, and BLX18012.6.10.2 CBZ and CBNZ18212.6.10.3 IT18312.6.10.4 TBB and TBH18412.6.11 Miscellaneous Instructions18712.6.11.1 BKPT18812.6.11.2 CPS18812.6.11.3 DMB18912.6.11.4 DSB19012.6.11.5 ISB19012.6.11.6 MRS19112.6.11.7 MSR19112.6.11.8 NOP19212.6.11.9 SEV19312.6.11.10 SVC19312.6.11.11 WFE19412.6.11.12 WFI19412.7 Cortex-M4 Core Peripherals19512.7.1 Peripherals19512.7.2 Address Map19512.8 Nested Vectored Interrupt Controller (NVIC)19612.8.1 Level-sensitive Interrupts19612.8.1.1 Hardware and Software Control of Interrupts19612.8.2 NVIC Design Hints and Tips19612.8.2.1 NVIC Programming Hints19712.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface19912.8.3.1 Interrupt Set-enable Registers20012.8.3.2 Interrupt Clear-enable Registers20112.8.3.3 Interrupt Set-pending Registers20212.8.3.4 Interrupt Clear-pending Registers20312.8.3.5 Interrupt Active Bit Registers20412.8.3.6 Interrupt Priority Registers20512.8.3.7 Software Trigger Interrupt Register20612.9 System Control Block (SCB)20712.9.1 System Control Block (SCB) User Interface20812.9.1.1 Auxiliary Control Register20912.9.1.2 CPUID Base Register21012.9.1.3 Interrupt Control and State Register21112.9.1.4 Vector Table Offset Register21312.9.1.5 Application Interrupt and Reset Control Register21412.9.1.6 System Control Register21612.9.1.7 Configuration and Control Register21712.9.1.8 System Handler Priority Registers21912.9.1.9 System Handler Priority Register 122012.9.1.10 System Handler Priority Register 222112.9.1.11 System Handler Priority Register 322212.9.1.12 System Handler Control and State Register22312.9.1.13 Configurable Fault Status Register22512.9.1.14 Configurable Fault Status Register (Byte Access)22912.9.1.15 Hard Fault Status Register23012.9.1.16 MemManage Fault Address Register23112.9.1.17 Bus Fault Address Register23212.10 System Timer (SysTick)23312.10.1 System Timer (SysTick) User Interface23412.10.1.1 SysTick Control and Status23512.10.1.2 SysTick Reload Value Registers23612.10.1.3 SysTick Current Value Register23712.10.1.4 SysTick Calibration Value Register23812.11 Memory Protection Unit (MPU)23912.11.1 MPU Access Permission Attributes23912.11.1.1 MPU Mismatch24112.11.1.2 Updating an MPU Region24112.11.1.3 Updating an MPU Region Using Separate Words24112.11.1.4 Updating an MPU Region Using Multi-word Writes24212.11.1.5 Subregions24312.11.1.6 Example of SRD Use24312.11.1.7 MPU Design Hints And Tips24312.11.2 Memory Protection Unit (MPU) User Interface24512.11.2.1 MPU Type Register24612.11.2.2 MPU Control Register24712.11.2.3 MPU Region Number Register24912.11.2.4 MPU Region Base Address Register25012.11.2.5 MPU Region Attribute and Size Register25112.11.2.6 MPU Region Base Address Register Alias 125312.11.2.7 MPU Region Attribute and Size Register Alias 125412.11.2.8 MPU Region Base Address Register Alias 225612.11.2.9 MPU Region Attribute and Size Register Alias 225712.11.2.10 MPU Region Base Address Register Alias 325912.11.2.11 MPU Region Attribute and Size Register Alias 326012.12 Glossary26213. Debug and Test Features26713.1 Description26713.2 Embedded Characteristics26713.3 Application Examples26813.3.1 Debug Environment26813.3.2 Test Environment26813.4 Debug and Test Pin Description26913.5 Functional Description27013.5.1 Test Pin27013.5.2 Debug Architecture27013.5.3 Serial Wire/JTAG Debug Port (SWJ-DP)27013.5.3.1 SW-DP and JTAG-DP Selection Mechanism27113.5.4 FPB (Flash Patch Breakpoint)27113.5.5 DWT (Data Watchpoint and Trace)27113.5.6 ITM (Instrumentation Trace Macrocell)27213.5.6.1 How to Configure the ITM27213.5.6.2 Asynchronous Mode27213.5.6.3 5.4.3. How to Configure the TPIU27313.5.7 IEEE® 1149.1 JTAG Boundary Scan27313.5.7.1 JTAG Boundary-scan Register27313.5.8 ID Code Register27414. Reset Controller (RSTC)27514.1 Description27514.2 Embedded Characteristics27514.3 Block Diagram27514.4 Functional Description27614.4.1 Reset Controller Overview27614.4.2 NRST Manager27614.4.2.1 NRST Signal or Interrupt27614.4.2.2 NRST External Reset Control27714.4.3 Brownout Manager27714.4.4 Reset States27714.4.4.1 General Reset27714.4.4.2 Backup Reset27814.4.4.3 User Reset27814.4.4.4 Software Reset27814.4.4.5 Watchdog Reset27914.4.5 Reset State Priorities28014.4.6 Reset Controller Status Register28114.5 Reset Controller (RSTC) User Interface28214.5.1 Reset Controller Control Register28314.5.2 Reset Controller Status Register28414.5.3 Reset Controller Mode Register28515. Real-time Timer (RTT)28615.1 Description28615.2 Embedded Characteristics28615.3 Block Diagram28615.4 Functional Description28715.5 Real-time Timer (RTT) User Interface28915.5.1 Real-time Timer Mode Register29015.5.2 Real-time Timer Alarm Register29115.5.3 Real-time Timer Value Register29215.5.4 Real-time Timer Status Register29316. Real-time Clock (RTC)29416.1 Description29416.2 Embedded Characteristics29416.3 Block Diagram29516.4 Product Dependencies29516.4.1 Power Management29516.4.2 Interrupt29516.5 Functional Description29516.5.1 Reference Clock29516.5.2 Timing29516.5.3 Alarm29616.5.4 Error Checking when Programming29616.5.5 RTC Internal Free Running Counter Error Checking29616.5.6 Updating Time/Calendar29716.5.7 RTC Accurate Clock Calibration29916.5.8 Waveform Generation29916.6 Real-time Clock (RTC) User Interface30116.6.1 RTC Control Register30216.6.2 RTC Mode Register30316.6.3 RTC Time Register30616.6.4 RTC Calendar Register30716.6.5 RTC Time Alarm Register30816.6.6 RTC Calendar Alarm Register30916.6.7 RTC Status Register31016.6.8 RTC Status Clear Command Register31116.6.9 RTC Interrupt Enable Register31216.6.10 RTC Interrupt Disable Register31316.6.11 RTC Interrupt Mask Register31416.6.12 RTC Valid Entry Register31517. Watchdog Timer (WDT)31617.1 Description31617.2 Embedded Characteristics31617.3 Block Diagram31717.4 Functional Description31817.5 Watchdog Timer (WDT) User Interface32017.5.1 Watchdog Timer Control Register32117.5.2 Watchdog Timer Mode Register32217.5.3 Watchdog Timer Status Register32418. Supply Controller (SUPC)32518.1 Embedded Characteristics32518.2 Block Diagram32618.3 Supply Controller Functional Description32718.3.1 Supply Controller Overview32718.3.2 Slow Clock Generator32818.3.3 Core Voltage Regulator Control/Backup Low-power Mode32818.3.4 Supply Monitor32818.3.5 Backup Power Supply Reset32918.3.5.1 Raising the Backup Power Supply32918.3.6 Core Reset33018.3.6.1 Supply Monitor Reset33018.3.6.2 Brownout Detector Reset33118.3.7 Wake-up Sources33118.3.7.1 Wake-up Inputs33118.3.7.2 Low-power Tamper Detection and Anti-Tampering33218.3.7.3 Clock Alarms33418.3.7.4 Supply Monitor Detection33418.3.8 Register Write Protection33418.3.9 Register Bits in Backup Domain (VDDIO)33518.4 Supply Controller (SUPC) User Interface33618.4.1 System Controller (SYSC) User Interface33618.4.2 Supply Controller (SUPC) User Interface33618.4.3 Supply Controller Control Register33718.4.4 Supply Controller Supply Monitor Mode Register33818.4.5 Supply Controller Mode Register33918.4.6 Supply Controller Wake-up Mode Register34018.4.7 Supply Controller Wake-up Inputs Register34218.4.8 Supply Controller Status Register34318.4.9 System Controller Write Protection Mode Register34519. General-Purpose Backup Registers (GPBR)34619.1 Description34619.2 Embedded Characteristics34619.3 General Purpose Backup Registers (GPBR) User Interface34719.3.1 General Purpose Backup Register x34820. Enhanced Embedded Flash Controller (EEFC)34920.1 Description34920.2 Embedded Characteristics34920.3 Product Dependencies34920.3.1 Power Management34920.3.2 Interrupt Sources34920.4 Functional Description35020.4.1 Embedded Flash Organization35020.4.2 Read Operations35120.4.2.1 128-bit or 64-bit Access Mode35120.4.2.2 Code Read Optimization35120.4.2.3 Code Loop Optimization35220.4.2.4 Data Read Optimization35320.4.3 Flash Commands35420.4.3.1 Get Flash Descriptor Command35620.4.3.2 Write Commands35620.4.3.3 Erase Commands36020.4.3.4 Lock Bit Protection36120.4.3.5 GPNVM Bit36220.4.3.6 Calibration Bit36220.4.3.7 Security Bit Protection36320.4.3.8 Unique Identifier36320.4.3.9 User Signature36320.5 Enhanced Embedded Flash Controller (EEFC) User Interface36520.5.1 EEFC Flash Mode Register36620.5.2 EEFC Flash Command Register36720.5.3 EEFC Flash Status Register36920.5.4 EEFC Flash Result Register37021. Fast Flash Programming Interface (FFPI)37121.1 Description37121.2 Embedded Characteristics37121.3 Parallel Fast Flash Programming37221.3.1 Device Configuration37221.3.2 Signal Names37321.3.3 Entering Programming Mode37421.3.4 Programmer Handshaking37421.3.4.1 Write Handshaking37421.3.4.2 Read Handshaking37521.3.5 Device Operations37621.3.5.1 Flash Read Command37721.3.5.2 Flash Write Command37721.3.5.3 Flash Full Erase Command37821.3.5.4 Flash Lock Commands37821.3.5.5 Flash General-purpose NVM Commands37821.3.5.6 Flash Security Bit Command37921.3.5.7 Memory Write Command37921.3.5.8 Get Version Command38022. Cortex-M Cache Controller (CMCC)38122.1 Description38122.2 Embedded Characteristics38122.3 Block Diagram38222.4 Functional Description38222.4.1 Cache Operation38222.4.2 Cache Maintenance38222.4.2.1 Cache Invalidate by Line Operation38222.4.2.2 Cache Invalidate All Operation38322.4.3 Cache Performance Monitoring38322.5 Cortex M Cache Controller (CMCC) User Interface38422.5.1 Cache Controller Type Register38522.5.2 Cache Controller Configuration Register38722.5.3 Cache Controller Control Register38822.5.4 Cache Controller Status Register38922.5.5 Cache Controller Maintenance Register 039022.5.6 Cache Controller Maintenance Register 139122.5.7 Cache Controller Monitor Configuration Register39222.5.8 Cache Controller Monitor Enable Register39322.5.9 Cache Controller Monitor Control Register39422.5.10 Cache Controller Monitor Status Register39523. Cyclic Redundancy Check Calculation Unit (CRCCU)39623.1 Description39623.2 Embedded Characteristics39623.3 CRCCU Block Diagram39723.4 Product Dependencies39823.4.1 Power Management39823.4.2 Interrupt Source39823.5 CRCCU Functional Description39923.5.1 CRC Calculation Unit39923.5.2 CRC Calculation Unit Operation39923.6 Transfer Control Registers Memory Mapping40023.6.1 Transfer Address Register40123.6.2 Transfer Control Register40223.6.3 Transfer Reference Register40323.7 Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface40423.7.1 CRCCU Descriptor Base Address Register40523.7.2 CRCCU DMA Enable Register40623.7.3 CRCCU DMA Disable Register40723.7.4 CRCCU DMA Status Register40823.7.5 CRCCU DMA Interrupt Enable Register40923.7.6 CRCCU DMA Interrupt Disable Register41023.7.7 CRCCU DMA Interrupt Mask Register41123.7.8 CRCCU DMA Interrupt Status Register41223.7.9 CRCCU Control Register41323.7.10 CRCCU Mode Register41423.7.11 CRCCU Status Register41523.7.12 CRCCU Interrupt Enable Register41623.7.13 CRCCU Interrupt Disable Register41723.7.14 CRCCU Interrupt Mask Register41823.7.15 CRCCU Interrupt Status Register41924. Boot Program42024.1 Description42024.2 Hardware and Software Constraints42024.3 Flow Diagram42024.4 Device Initialization42124.5 SAM-BA Monitor42224.5.1 UART0 Serial Port42324.5.2 Xmodem Protocol42324.5.3 USB Device Port42324.5.3.1 Enumeration Process42424.5.3.2 Communication Endpoints42424.5.4 In Application Programming (IAP) Feature42525. Bus Matrix (MATRIX)42625.1 Description42625.2 Master/Slave Management42625.2.1 Matrix Masters42625.2.2 Matrix Slaves42625.2.3 Master to Slave Access42725.3 Memory Mapping42725.4 Special Bus Granting Techniques42725.4.1 No Default Master42725.4.2 Last Access Master42725.4.3 Fixed Default Master42725.5 Arbitration42825.5.1 Arbitration Rules42825.5.1.1 Undefined Length Burst Arbitration42825.5.1.2 Slot Cycle Limit Arbitration42825.5.2 Round-Robin Arbitration42925.5.2.1 Round-Robin arbitration without default master42925.5.2.2 Round-Robin arbitration with last access master42925.5.2.3 Round-Robin arbitration with fixed default master42925.5.3 Fixed Priority Arbitration42925.6 System I/O Configuration42925.7 Register Write Protection43025.8 Bus Matrix (MATRIX) (MATRIX) User Interface43125.8.1 Bus Matrix Master Configuration Registers43225.8.2 Bus Matrix Slave Configuration Registers43325.8.3 Bus Matrix Priority Registers For Slaves43425.8.4 System I/O Configuration Register43525.8.5 SMC NAND Flash Chip Select Configuration Register43525.8.6 Write Protection Mode Register43725.8.7 Write Protection Status Register43826. Static Memory Controller (SMC)43926.1 Description43926.2 Embedded Characteristics43926.3 I/O Lines Description44026.4 Product Dependencies44026.4.1 I/O Lines44026.4.2 Power Management44026.5 External Memory Mapping44026.6 Connection to External Devices44126.6.1 Data Bus Width44126.6.1.1 NAND Flash Support44126.7 Application Example44326.7.1 Implementation Examples44326.7.1.1 8-bit NAND Flash44426.7.1.2 NOR Flash44526.8 Standard Read and Write Protocols44526.8.1 Read Waveforms44526.8.1.1 NRD Waveform44626.8.1.2 NCS Waveform44626.8.1.3 Read Cycle44626.8.1.4 Null Delay Setup and Hold44726.8.1.5 Null Pulse44726.8.2 Read Mode44726.8.2.1 Read is Controlled by NRD (READ_MODE = 1):44726.8.2.2 Read is Controlled by NCS (READ_MODE = 0)44826.8.3 Write Waveforms44926.8.3.1 NWE Waveforms44926.8.3.2 NCS Waveforms44926.8.3.3 Write Cycle44926.8.3.4 Null Delay Setup and Hold45026.8.3.5 Null Pulse45026.8.4 Write Mode45026.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1):45026.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0)45126.8.5 Write Protected Registers45126.8.6 Coding Timing Parameters45226.8.7 Reset Values of Timing Parameters45226.8.8 Usage Restriction45226.9 Scrambling/Unscrambling Function45326.10 Automatic Wait States45326.10.1 Chip Select Wait States45326.10.2 Early Read Wait State45426.10.3 Reload User Configuration Wait State45626.10.3.1 User Procedure45626.10.3.2 Slow Clock Mode Transition45726.10.4 Read to Write Wait State45726.11 Data Float Wait States45726.11.1 READ_MODE45726.11.2 TDF Optimization Enabled (TDF_MODE = 1)45826.11.3 TDF Optimization Disabled (TDF_MODE = 0)45926.12 External Wait46126.12.1 Restriction46126.12.2 Frozen Mode46226.12.3 Ready Mode46426.12.4 NWAIT Latency and Read/Write Timings46626.13 Slow Clock Mode46726.13.1 Slow Clock Mode Waveforms46726.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode46826.14 Asynchronous Page Mode46926.14.1 Protocol and Timings in Page Mode46926.14.2 Page Mode Restriction47026.14.3 Sequential and Non-sequential Accesses47026.15 Static Memory Controller (SMC) User Interface47226.15.1 SMC Setup Register47326.15.2 SMC Pulse Register47426.15.3 SMC Cycle Register47526.15.4 SMC MODE Register47626.15.5 SMC OCMS Mode Register47826.15.6 SMC OCMS Key1 Register47926.15.7 SMC OCMS Key2 Register48026.15.8 SMC Write Protect Mode Register48126.15.9 SMC Write Protect Status Register48227. Peripheral DMA Controller (PDC)48327.1 Description48327.2 Embedded Characteristics48327.3 Block Diagram48427.4 Functional Description48527.4.1 Configuration48527.4.2 Memory Pointers48527.4.3 Transfer Counters48527.4.4 Data Transfers48627.4.5 PDC Flags and Peripheral Status Register48627.4.5.1 Receive Transfer End48627.4.5.2 Transmit Transfer End48627.4.5.3 Receive Buffer Full48627.4.5.4 Transmit Buffer Empty48627.5 Peripheral DMA Controller (PDC) User Interface48727.5.1 Receive Pointer Register48827.5.2 Receive Counter Register48927.5.3 Transmit Pointer Register49027.5.4 Transmit Counter Register49127.5.5 Receive Next Pointer Register49227.5.6 Receive Next Counter Register49327.5.7 Transmit Next Pointer Register49427.5.8 Transmit Next Counter Register49527.5.9 Transfer Control Register49627.5.10 Transfer Status Register49728. Clock Generator49828.1 Description49828.2 Embedded Characteristics49828.3 Block Diagram49928.4 Slow Clock49928.4.1 Slow Clock RC Oscillator49928.4.2 Slow Clock Crystal Oscillator50028.5 Main Clock50128.5.1 Fast RC Oscillator50128.5.2 Fast RC Oscillator Clock Frequency Adjustment50228.5.3 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator50228.5.4 Main Clock Oscillator Selection50328.5.5 Switching Main Clock between the Main RC Oscillator and Fast Crystal Oscillator50328.5.6 Software Sequence to Detect the Presence of Fast Crystal50328.5.7 Main Clock Frequency Counter50428.6 Divider and PLL Block50528.6.1 Divider and Phase Lock Loop Programming50529. Power Management Controller (PMC)50729.1 Description50729.2 Embedded Characteristics50729.3 Block Diagram50829.4 Master Clock Controller50829.5 Processor Clock Controller50929.6 SysTick Clock50929.7 USB Clock Controller50929.8 Peripheral Clock Controller50929.9 Free-Running Processor Clock51029.10 Programmable Clock Output Controller51029.11 Fast Startup51029.12 Start-up from Embedded Flash51129.13 Main Clock Failure Detector51229.14 Programming Sequence51329.15 Clock Switching Details51529.15.1 Master Clock Switching Timings51529.15.2 Clock Switching Waveforms51629.16 Register Write Protection51929.17 Power Management Controller (PMC) User Interface52029.17.1 PMC System Clock Enable Register52229.17.2 PMC System Clock Disable Register52329.17.3 PMC System Clock Status Register52429.17.4 PMC Peripheral Clock Enable Register 052529.17.5 PMC Peripheral Clock Disable Register 052629.17.6 PMC Peripheral Clock Status Register 052729.17.7 PMC Clock Generator Main Oscillator Register52829.17.8 PMC Clock Generator Main Clock Frequency Register53029.17.9 PMC Clock Generator PLLA Register53129.17.10 PMC Clock Generator PLLB Register53229.17.11 PMC Master Clock Register53329.17.12 PMC USB Clock Register53529.17.13 PMC Programmable Clock Register53629.17.14 PMC Interrupt Enable Register53729.17.15 PMC Interrupt Disable Register53829.17.16 PMC Status Register53929.17.17 PMC Interrupt Mask Register54129.17.18 PMC Fast Start-up Mode Register54229.17.19 PMC Fast Start-up Polarity Register54329.17.20 PMC Fault Output Clear Register54529.17.21 PMC Write Protection Mode Register54629.17.22 PMC Write Protection Status Register54729.17.23 PMC Peripheral Clock Enable Register 154829.17.24 PMC Peripheral Clock Disable Register 154929.17.25 PMC Peripheral Clock Status Register 155029.17.26 PMC Oscillator Calibration Register55130. Chip Identifier (CHIPID)55230.1 Description55230.2 Embedded Characteristics55230.3 Chip Identifier (CHIPID) User Interface55330.3.1 Chip ID Register55430.3.2 Chip ID Extension Register55731. Parallel Input/Output Controller (PIO)55831.1 Description55831.2 Embedded Characteristics55831.3 Block Diagram55931.4 Product Dependencies56131.4.1 Pin Multiplexing56131.4.2 External Interrupt Lines56131.4.3 Power Management56131.4.4 Interrupt Generation56131.5 Functional Description56231.5.1 Pull-up and Pull-down Resistor Control56331.5.2 I/O Line or Peripheral Function Selection56331.5.3 Peripheral A or B or C or D Selection56331.5.4 Output Control56431.5.5 Synchronous Data Output56431.5.6 Multi-Drive Control (Open Drain)56431.5.7 Output Line Timings56431.5.8 Inputs56531.5.9 Input Glitch and Debouncing Filters56531.5.10 Input Edge/Level Interrupt56631.5.10.1 Example56731.5.10.2 Interrupt Mode Configuration56831.5.10.3 Edge or Level Detection Configuration56831.5.10.4 Falling/Rising Edge or Low/High-Level Detection Configuration56831.5.11 I/O Lines Lock56831.5.12 Programmable Schmitt Trigger56831.5.13 Parallel Capture Mode56931.5.13.1 Overview56931.5.13.2 Functional Description56931.5.13.3 Restrictions57131.5.13.4 Programming Sequence57131.5.14 Register Write Protection57331.6 I/O Lines Programming Example57431.7 Parallel Input/Output Controller (PIO) User Interface57531.7.1 PIO Enable Register57831.7.2 PIO Disable Register57831.7.3 PIO Status Register57931.7.4 PIO Output Enable Register58031.7.5 PIO Output Disable Register58031.7.6 PIO Output Status Register58131.7.7 PIO Input Filter Enable Register58231.7.8 PIO Input Filter Disable Register58231.7.9 PIO Input Filter Status Register58331.7.10 PIO Set Output Data Register58431.7.11 PIO Clear Output Data Register58431.7.12 PIO Output Data Status Register58531.7.13 PIO Pin Data Status Register58631.7.14 PIO Interrupt Enable Register58731.7.15 PIO Interrupt Disable Register58731.7.16 PIO Interrupt Mask Register58831.7.17 PIO Interrupt Status Register58931.7.18 PIO Multi-driver Enable Register59031.7.19 PIO Multi-driver Disable Register59031.7.20 PIO Multi-driver Status Register59131.7.21 PIO Pull-Up Disable Register59231.7.22 PIO Pull-Up Enable Register59231.7.23 PIO Pull-Up Status Register59331.7.24 PIO Peripheral ABCD Select Register 159431.7.25 PIO Peripheral ABCD Select Register 259531.7.26 PIO Input Filter Slow Clock Disable Register59631.7.27 PIO Input Filter Slow Clock Enable Register59631.7.28 PIO Input Filter Slow Clock Status Register59731.7.29 PIO Slow Clock Divider Debouncing Register59831.7.30 PIO Pad Pull-Down Disable Register59931.7.31 PIO Pad Pull-Down Enable Register59931.7.32 PIO Pad Pull-Down Status Register60031.7.33 PIO Output Write Enable Register60131.7.34 PIO Output Write Disable Register60131.7.35 PIO Output Write Status Register60231.7.36 PIO Additional Interrupt Modes Enable Register60331.7.37 PIO Additional Interrupt Modes Disable Register60331.7.38 PIO Additional Interrupt Modes Mask Register60431.7.39 PIO Edge Select Register60531.7.40 PIO Level Select Register60531.7.41 PIO Edge/Level Status Register60631.7.42 PIO Falling Edge/Low-Level Select Register60631.7.43 PIO Rising Edge/High-Level Select Register60731.7.44 PIO Fall/Rise - Low/High Status Register60731.7.45 PIO Lock Status Register60831.7.46 PIO Write Protection Mode Register60931.7.47 PIO Write Protection Status Register61031.7.48 PIO Schmitt Trigger Register61131.7.49 PIO Parallel Capture Mode Register61231.7.50 PIO Parallel Capture Interrupt Enable Register61331.7.51 PIO Parallel Capture Interrupt Disable Register61431.7.52 PIO Parallel Capture Interrupt Mask Register61531.7.53 PIO Parallel Capture Interrupt Status Register61631.7.54 PIO Parallel Capture Reception Holding Register61732. Synchronous Serial Controller (SSC)61832.1 Description61832.2 Embedded Characteristics61832.3 Block Diagram61932.4 Application Block Diagram61932.5 Pin Name List62032.6 Product Dependencies62032.6.1 I/O Lines62032.6.2 Power Management62032.6.3 Interrupt62032.7 Functional Description62132.7.1 Clock Management62132.7.1.1 Clock Divider62232.7.1.2 Transmitter Clock Management62332.7.1.3 Receiver Clock Management62332.7.1.4 Serial Clock Ratio Considerations62432.7.2 Transmitter Operations62432.7.3 Receiver Operations62532.7.4 Start62632.7.5 Frame Sync62832.7.5.1 Frame Sync Data62832.7.5.2 Frame Sync Edge Detection62832.7.6 Receive Compare Modes62832.7.6.1 Compare Functions62832.7.7 Data Format62932.7.8 Loop Mode63132.7.9 Interrupt63132.8 SSC Application Examples63232.8.1 Write Protection Registers63432.9 Synchronous Serial Controller (SSC) User Interface63532.9.1 SSC Control Register63632.9.2 SSC Clock Mode Register63732.9.3 SSC Receive Clock Mode Register63832.9.4 SSC Receive Frame Mode Register64032.9.5 SSC Transmit Clock Mode Register64232.9.6 SSC Transmit Frame Mode Register64432.9.7 SSC Receive Holding Register64632.9.8 SSC Transmit Holding Register64732.9.9 SSC Receive Synchronization Holding Register64832.9.10 SSC Transmit Synchronization Holding Register64932.9.11 SSC Receive Compare 0 Register65032.9.12 SSC Receive Compare 1 Register65132.9.13 SSC Status Register65232.9.14 SSC Interrupt Enable Register65432.9.15 SSC Interrupt Disable Register65632.9.16 SSC Interrupt Mask Register65832.9.17 SSC Write Protect Mode Register66032.9.18 SSC Write Protect Status Register66133. Serial Peripheral Interface (SPI)66233.1 Description66233.2 Embedded Characteristics66333.3 Block Diagram66433.4 Application Block Diagram66533.5 Signal Description66533.6 Product Dependencies66533.6.1 I/O Lines66533.6.2 Power Management66633.6.3 Interrupt66633.6.4 Peripheral DMA Controller (PDC)66633.7 Functional Description66633.7.1 Modes of Operation66633.7.2 Data Transfer66733.7.3 Master Mode Operations66833.7.3.1 Master Mode Block Diagram66933.7.3.2 Master Mode Flow Diagram67033.7.3.3 Clock Generation67233.7.3.4 Transfer Delays67233.7.3.5 Peripheral Selection67333.7.3.6 SPI Peripheral DMA Controller (PDC)673Transfer Size67433.7.3.7 Peripheral Chip Select Decoding67433.7.3.8 Peripheral Deselection without PDC67533.7.3.9 Peripheral Deselection with PDC67533.7.3.10 Mode Fault Detection67633.7.4 SPI Slave Mode67733.7.5 Register Write Protection67933.8 Serial Peripheral Interface (SPI) User Interface68033.8.1 SPI Control Register68133.8.2 SPI Mode Register68233.8.3 SPI Receive Data Register68433.8.4 SPI Transmit Data Register68533.8.5 SPI Status Register68633.8.6 SPI Interrupt Enable Register68833.8.7 SPI Interrupt Disable Register68933.8.8 SPI Interrupt Mask Register69033.8.9 SPI Chip Select Register69133.8.10 SPI Write Protection Mode Register69433.8.11 SPI Write Protection Status Register69534. Two-wire Interface (TWI)69634.1 Description69634.2 Embedded Characteristics69634.3 List of Abbreviations69734.4 Block Diagram69734.5 Application Block Diagram69834.5.1 I/O Lines Description69834.6 Product Dependencies69834.6.1 I/O Lines69834.6.2 Power Management69834.6.3 Interrupt69934.7 Functional Description70034.7.1 Transfer Format70034.7.2 Modes of Operation70034.8 Master Mode70134.8.1 Definition70134.8.2 Application Block Diagram70134.8.3 Programming Master Mode70134.8.4 Master Transmitter Mode70134.8.5 Master Receiver Mode70334.8.6 Internal Address70434.8.6.1 7-bit Slave Addressing70434.8.6.2 10-bit Slave Addressing70534.8.7 Using the Peripheral DMA Controller (PDC)70534.8.7.1 Data Transmit with the PDC70534.8.7.2 Data Receive with the PDC70634.8.8 SMBUS Quick Command (Master Mode Only)70634.8.9 Read-write Flowcharts70734.9 Multi-master Mode71334.9.1 Definition71334.9.2 Different Multi-master Modes71334.9.2.1 TWI as Master Only71334.9.2.2 TWI as Master or Slave71334.10 Slave Mode71634.10.1 Definition71634.10.2 Application Block Diagram71634.10.3 Programming Slave Mode71634.10.4 Receiving Data71634.10.4.1 Read Sequence71634.10.4.2 Write Sequence71734.10.4.3 Clock Synchronization Sequence71734.10.4.4 General Call71734.10.5 Data Transfer71734.10.5.1 Read Operation71734.10.5.2 Write Operation71834.10.5.3 General Call71834.10.5.4 Clock Synchronization71934.10.5.5 Reversal after a Repeated Start72034.10.6 Using the Peripheral DMA Controller (PDC) in Slave Mode72134.10.6.1 Data Transmit with the PDC in Slave Mode72134.10.6.2 Data Receive with the PDC in Slave Mode72134.10.7 Read Write Flowcharts72234.11 Two-wire Interface (TWI) User Interface72334.11.1 TWI Control Register72434.11.2 TWI Master Mode Register72634.11.3 TWI Slave Mode Register72734.11.4 TWI Internal Address Register72834.11.5 TWI Clock Waveform Generator Register72934.11.6 TWI Status Register73034.11.7 TWI Interrupt Enable Register73334.11.8 TWI Interrupt Disable Register73434.11.9 TWI Interrupt Mask Register73534.11.10 TWI Receive Holding Register73634.11.11 TWI Transmit Holding Register73735. Universal Asynchronous Receiver Transmitter (UART)73835.1 Description73835.2 Embedded Characteristics73835.3 Block Diagram73835.4 Product Dependencies73935.4.1 I/O Lines73935.4.2 Power Management73935.4.3 Interrupt Source73935.5 UART Operations73935.5.1 Baud Rate Generator73935.5.2 Receiver74035.5.2.1 Receiver Reset, Enable and Disable74035.5.2.2 Start Detection and Data Sampling74035.5.2.3 Receiver Ready74135.5.2.4 Receiver Overrun74135.5.2.5 Parity Error74135.5.2.6 Receiver Framing Error74235.5.3 Transmitter74235.5.3.1 Transmitter Reset, Enable and Disable74235.5.3.2 Transmit Format74235.5.3.3 Transmitter Control74335.5.4 Peripheral DMA Controller (PDC)74335.5.5 Test Modes74335.6 Universal Asynchronous Receiver Transmitter (UART) User Interface74535.6.1 UART Control Register74635.6.2 UART Mode Register74735.6.3 UART Interrupt Enable Register74835.6.4 UART Interrupt Disable Register74935.6.5 UART Interrupt Mask Register75035.6.6 UART Status Register75135.6.7 UART Receiver Holding Register75335.6.8 UART Transmit Holding Register75435.6.9 UART Baud Rate Generator Register75536. Universal Synchronous Asynchronous Receiver Transceiver (USART)75636.1 Description75636.2 Embedded Characteristics75636.3 Block Diagram75736.4 Application Block Diagram75836.5 I/O Lines Description75936.6 Product Dependencies76036.6.1 I/O Lines76036.6.2 Power Management76036.6.3 Interrupt76036.7 Functional Description76136.7.1 Baud Rate Generator76136.7.1.1 Baud Rate in Asynchronous Mode76136.7.1.2 Fractional Baud Rate in Asynchronous Mode76236.7.1.3 Baud Rate in Synchronous Mode or SPI Mode76336.7.1.4 Baud Rate in ISO 7816 Mode76336.7.2 Receiver and Transmitter Control76536.7.3 Synchronous and Asynchronous Modes76536.7.3.1 Transmitter Operations76536.7.3.2 Manchester Encoder76636.7.3.3 Asynchronous Receiver76836.7.3.4 Manchester Decoder76936.7.3.5 Radio Interface: Manchester Encoded USART Application77136.7.3.6 Synchronous Receiver77236.7.3.7 Receiver Operations77336.7.3.8 Parity77336.7.3.9 Multidrop Mode77436.7.3.10 Transmitter Timeguard77436.7.3.11 Receiver Time-out77536.7.3.12 Framing Error77736.7.3.13 Transmit Break77736.7.3.14 Receive Break77836.7.3.15 Hardware Handshaking77836.7.4 ISO7816 Mode77936.7.4.1 ISO7816 Mode Overview77936.7.4.2 Protocol T = 078036.7.4.3 Protocol T = 178136.7.5 IrDA Mode78136.7.5.1 IrDA Modulation78236.7.5.2 IrDA Baud Rate78236.7.5.3 IrDA Demodulator78336.7.6 RS485 Mode78336.7.7 Modem Mode78536.7.8 SPI Mode78636.7.8.1 Modes of Operation78636.7.8.2 Baud Rate78636.7.8.3 Data Transfer78736.7.8.4 Receiver and Transmitter Control78836.7.8.5 Character Transmission78836.7.8.6 Character Reception78936.7.8.7 Receiver Timeout78936.7.9 Test Modes78936.7.9.1 Normal Mode78936.7.9.2 Automatic Echo Mode79036.7.9.3 Local Loopback Mode79036.7.9.4 Remote Loopback Mode79036.7.10 Register Write Protection79136.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface79236.8.1 USART Control Register79336.8.2 USART Control Register (SPI_MODE)79636.8.3 USART Mode Register79836.8.4 USART Mode Register (SPI_MODE)80236.8.5 USART Interrupt Enable Register80436.8.6 USART Interrupt Enable Register (SPI_MODE)80636.8.7 USART Interrupt Disable Register80736.8.8 USART Interrupt Disable Register (SPI_MODE)80936.8.9 USART Interrupt Mask Register81036.8.10 USART Interrupt Mask Register (SPI_MODE)81236.8.11 USART Channel Status Register81336.8.12 USART Channel Status Register (SPI_MODE)81636.8.13 USART Receive Holding Register81736.8.14 USART Transmit Holding Register81836.8.15 USART Baud Rate Generator Register81936.8.16 USART Receiver Time-out Register82036.8.17 USART Transmitter Timeguard Register82136.8.18 USART FI DI RATIO Register82236.8.19 USART Number of Errors Register82336.8.20 USART IrDA FILTER Register82436.8.21 USART Manchester Configuration Register82536.8.22 USART Write Protection Mode Register82736.8.23 USART Write Protection Status Register82837. Timer Counter (TC)82937.1 Description82937.2 Embedded Characteristics82937.3 Block Diagram83037.4 Pin Name List83137.5 Product Dependencies83137.5.1 I/O Lines83137.5.2 Power Management83237.5.3 Interrupt83237.5.4 Fault Output83237.6 Functional Description83237.6.1 TC Description83237.6.2 16-bit Counter83237.6.3 Clock Selection83237.6.4 Clock Control83437.6.5 TC Operating Modes83437.6.6 Trigger83437.6.7 Capture Operating Mode83537.6.8 Capture Registers A and B83537.6.9 Trigger Conditions83537.6.10 Waveform Operating Mode83737.6.11 Waveform Selection83737.6.11.1 WAVSEL = 0083937.6.11.2 WAVSEL = 1084037.6.11.3 WAVSEL = 0184137.6.11.4 WAVSEL = 1184237.6.12 External Event/Trigger Conditions84337.6.13 Output Controller84337.6.14 Quadrature Decoder Logic84337.6.14.1 Description84337.6.14.2 Input Pre-processing84437.6.14.3 Direction Status and Change Detection84737.6.14.4 Position and Rotation Measurement84837.6.14.5 Speed Measurement84937.6.15 2-bit Gray Up/Down Counter for Stepper Motor84937.6.16 Register Write Protection84937.6.17 Fault Mode85037.7 Timer Counter (TC) User Interface85137.7.1 TC Channel Control Register85237.7.2 TC Channel Mode Register: Capture Mode85337.7.3 TC Channel Mode Register: Waveform Mode85537.7.4 TC Stepper Motor Mode Register85937.7.5 TC Counter Value Register86037.7.6 TC Register A86137.7.7 TC Register B86237.7.8 TC Register C86337.7.9 TC Status Register86437.7.10 TC Interrupt Enable Register86637.7.11 TC Interrupt Disable Register86837.7.12 TC Interrupt Mask Register87037.7.13 TC Block Control Register87237.7.14 TC Block Mode Register87337.7.15 TC QDEC Interrupt Enable Register87637.7.16 TC QDEC Interrupt Disable Register87737.7.17 TC QDEC Interrupt Mask Register87837.7.18 TC QDEC Interrupt Status Register87937.7.19 TC Fault Mode Register88037.7.20 TC Write Protection Mode Register88138. High Speed MultiMedia Card Interface (HSMCI)88238.1 Description88238.2 Embedded Characteristics88238.3 Block Diagram88338.4 Application Block Diagram88438.5 Pin Name List88438.6 Product Dependencies88538.6.1 I/O Lines88538.6.2 Power Management88538.6.3 Interrupt88538.7 Bus Topology88538.8 High Speed MultiMedia Card Operations88838.8.1 Command - Response Operation88838.8.2 Data Transfer Operation89138.8.3 Read Operation89138.8.4 Write Operation89338.9 SD/SDIO Card Operation89638.9.1 SDIO Data Transfer Type89638.9.2 SDIO Interrupts89638.10 CE-ATA Operation89738.10.1 Executing an ATA Polling Command89738.10.2 Executing an ATA Interrupt Command89738.10.3 Aborting an ATA Command89738.10.4 CE-ATA Error Recovery89738.11 HSMCI Boot Operation Mode89838.11.1 Boot Procedure, Processor Mode89838.12 HSMCI Transfer Done Timings89838.12.1 Definition89838.12.2 Read Access89838.12.3 Write Access89938.13 Register Write Protection90038.14 High Speed MultiMedia Card Interface (HSMCI) User Interface90138.14.1 HSMCI Control Register90238.14.2 HSMCI Mode Register90338.14.3 HSMCI Data Timeout Register90538.14.4 HSMCI SDCard/SDIO Register90638.14.5 HSMCI Argument Register90738.14.6 HSMCI Command Register90838.14.7 HSMCI Block Register91038.14.8 HSMCI Completion Signal Timeout Register91138.14.9 HSMCI Response Register91238.14.10 HSMCI Receive Data Register91338.14.11 HSMCI Transmit Data Register91438.14.12 HSMCI Status Register91538.14.13 HSMCI Interrupt Enable Register91938.14.14 HSMCI Interrupt Disable Register92138.14.15 HSMCI Interrupt Mask Register92338.14.16 HSMCI Configuration Register92538.14.17 HSMCI Write Protection Mode Register92638.14.18 HSMCI Write Protection Status Register92739. Pulse Width Modulation Controller (PWM)92839.1 Description92839.2 Embedded Characteristics92839.3 Block Diagram92939.4 I/O Lines Description93039.5 Product Dependencies93139.5.1 I/O Lines93139.5.2 Power Management93239.5.3 Interrupt Sources93239.5.4 Fault Inputs93239.6 Functional Description93339.6.1 PWM Clock Generator93339.6.2 PWM Channel93439.6.2.1 Channel Block Diagram93439.6.2.2 Comparator93539.6.2.3 2-bit Gray Up/Down Counter for Stepper Motor93739.6.2.4 Dead-Time Generator93839.6.2.5 Output Override93939.6.2.6 Fault Protection94039.6.2.7 Synchronous Channels94139.6.3 PWM Comparison Units94639.6.4 PWM Event Lines94839.6.5 PWM Controller Operations94939.6.5.1 Initialization94939.6.5.2 Source Clock Selection Criteria94939.6.5.3 Changing the Duty-Cycle, the Period and the Dead-Times94939.6.5.4 Changing the Synchronous Channels Update Period95039.6.5.5 Changing the Comparison Value and the Comparison Configuration95139.6.5.6 Interrupts95239.6.5.7 Register Write Protection95239.7 Pulse Width Modulation Controller (PWM) User Interface95439.7.1 PWM Clock Register95739.7.2 PWM Enable Register95839.7.3 PWM Disable Register95939.7.4 PWM Status Register96039.7.5 PWM Interrupt Enable Register 196139.7.6 PWM Interrupt Disable Register 196239.7.7 PWM Interrupt Mask Register 196339.7.8 PWM Interrupt Status Register 196439.7.9 PWM Sync Channels Mode Register96539.7.10 PWM Sync Channels Update Control Register96639.7.11 PWM Sync Channels Update Period Register96739.7.12 PWM Sync Channels Update Period Update Register96839.7.13 PWM Interrupt Enable Register 296939.7.14 PWM Interrupt Disable Register 297039.7.15 PWM Interrupt Mask Register 297139.7.16 PWM Interrupt Status Register 297239.7.17 PWM Output Override Value Register97339.7.18 PWM Output Selection Register97439.7.19 PWM Output Selection Set Register97539.7.20 PWM Output Selection Clear Register97639.7.21 PWM Output Selection Set Update Register97739.7.22 PWM Output Selection Clear Update Register97839.7.23 PWM Fault Mode Register97939.7.24 PWM Fault Status Register98039.7.25 PWM Fault Clear Register98139.7.26 PWM Fault Protection Value Register98239.7.27 PWM Fault Protection Enable Register98339.7.28 PWM Event Line x Register98439.7.29 PWM Stepper Motor Mode Register98539.7.30 PWM Write Protection Control Register98639.7.31 PWM Write Protection Status Register98839.7.32 PWM Comparison x Value Register98939.7.33 PWM Comparison x Value Update Register99039.7.34 PWM Comparison x Mode Register99139.7.35 PWM Comparison x Mode Update Register99239.7.36 PWM Channel Mode Register99339.7.37 PWM Channel Duty Cycle Register99539.7.38 PWM Channel Duty Cycle Update Register99639.7.39 PWM Channel Period Register99739.7.40 PWM Channel Period Update Register99839.7.41 PWM Channel Counter Register99939.7.42 PWM Channel Dead Time Register100039.7.43 PWM Channel Dead Time Update Register100140. USB Device Port (UDP)100240.1 Description100240.2 Embedded Characteristics100240.3 Block Diagram100340.3.1 Signal Description100340.4 Product Dependencies100340.4.1 I/O Lines100440.4.2 Power Management100440.4.3 Interrupt100440.5 Typical Connection100540.5.1 USB Device Transceiver100540.5.2 VBUS Monitoring100540.6 Functional Description100640.6.1 USB 2.0 Full-speed Introduction100640.6.1.1 USB 2.0 Full-speed Transfer Types100640.6.1.2 USB Bus Transactions100640.6.1.3 USB Transfer Event Definitions100740.6.2 Handling Transactions with USB 2.0 Device Peripheral100840.6.2.1 Setup Transaction100840.6.2.2 Data IN Transaction1008Using Endpoints Without Ping-pong Attributes1008Using Endpoints With Ping-pong Attribute100940.6.2.3 Data OUT Transaction1011Data OUT Transaction Without Ping-pong Attributes1011Using Endpoints With Ping-pong Attributes101240.6.2.4 Stall Handshake101440.6.2.5 Transmit Data Cancellation1015Endpoints Without Dual-Banks1015Endpoints With Dual-Banks101540.6.3 Controlling Device States101640.6.3.1 Not Powered State101640.6.3.2 Entering Attached State101740.6.3.3 From Powered State to Default State101740.6.3.4 From Default State to Address State101740.6.3.5 From Address State to Configured State101740.6.3.6 Entering in Suspend State101740.6.3.7 Receiving a Host Resume101840.6.3.8 Sending a Device Remote Wakeup101840.7 USB Device Port (UDP) User Interface101940.7.1 UDP Frame Number Register102040.7.2 UDP Global State Register102140.7.3 UDP Function Address Register102240.7.4 UDP Interrupt Enable Register102340.7.5 UDP Interrupt Disable Register102540.7.6 UDP Interrupt Mask Register102740.7.7 UDP Interrupt Status Register102940.7.8 UDP Interrupt Clear Register103140.7.9 UDP Reset Endpoint Register103240.7.10 UDP Endpoint Control and Status Register (CONTROL_BULK)103340.7.11 UDP Endpoint Control and Status Register (ISOCHRONOUS)103840.7.12 UDP FIFO Data Register104240.7.13 UDP Transceiver Control Register104341. Analog Comparator Controller (ACC)104441.1 Description104441.2 Embedded Characteristics104441.3 Block Diagram104541.4 Pin Name List104541.5 Product Dependencies104641.5.1 I/O Lines104641.5.2 Power Management104641.5.3 Interrupt104641.5.4 Fault Output104641.6 Functional Description104741.6.1 Description104741.6.2 Analog Settings104741.6.3 Output Masking Period104741.6.4 Fault Mode104741.6.5 Register Write Protection104741.7 Analog Comparator Controller (ACC) User Interface104841.7.1 ACC Control Register104941.7.2 ACC Mode Register105041.7.3 ACC Interrupt Enable Register105241.7.4 ACC Interrupt Disable Register105341.7.5 ACC Interrupt Mask Register105441.7.6 ACC Interrupt Status Register105541.7.7 ACC Analog Control Register105641.7.8 ACC Write Protection Mode Register105741.7.9 ACC Write Protection Status Register105842. Analog-to-Digital Converter (ADC)105942.1 Description105942.2 Embedded Characteristics106042.3 Block Diagram106142.4 Signal Description106242.5 Product Dependencies106342.5.1 Power Management106342.5.2 Interrupt Sources106342.5.3 Analog Inputs106342.5.4 Temperature Sensor106342.5.5 I/O Lines106342.5.6 Timer Triggers106442.5.7 PWM Event Line106442.5.8 Fault Output106442.5.9 Conversion Performances106442.6 Functional Description106442.6.1 Analog-to-Digital Conversion106442.6.2 Conversion Reference106642.6.3 Conversion Resolution106642.6.4 Conversion Results106642.6.5 Conversion Triggers106842.6.6 Sleep Mode and Conversion Sequencer106842.6.7 Comparison Window106942.6.8 Differential Inputs106942.6.9 Input Gain and Offset107042.6.10 ADC Timings107242.6.11 Automatic Calibration107342.6.12 Buffer Structure107342.6.13 Fault Output107342.6.14 Register Write Protection107442.7 Analog-to-Digital Converter (ADC) User Interface107542.7.1 ADC Control Register107642.7.2 ADC Mode Register107742.7.3 ADC Channel Sequence 1 Register108042.7.4 ADC Channel Sequence 2 Register108142.7.5 ADC Channel Enable Register108242.7.6 ADC Channel Disable Register108342.7.7 ADC Channel Status Register108442.7.8 ADC Last Converted Data Register108542.7.9 ADC Interrupt Enable Register108642.7.10 ADC Interrupt Disable Register108742.7.11 ADC Interrupt Mask Register108842.7.12 ADC Interrupt Status Register108942.7.13 ADC Overrun Status Register109042.7.14 ADC Extended Mode Register109142.7.15 ADC Compare Window Register109242.7.16 ADC Channel Gain Register109342.7.17 ADC Channel Offset Register109442.7.18 ADC Channel Data Register109542.7.19 ADC Analog Control Register109642.7.20 ADC Write Protection Mode Register109742.7.21 ADC Write Protection Status Register109843. Digital-to-Analog Converter Controller (DACC)109943.1 Description109943.2 Embedded Characteristics109943.3 Block Diagram110043.4 Signal Description110043.5 Product Dependencies110143.5.1 Power Management110143.5.2 Interrupt Sources110143.5.3 Conversion Performances110143.6 Functional Description110243.6.1 Digital-to-Analog Conversion110243.6.2 Conversion Results110243.6.3 Conversion Triggers110243.6.4 Conversion FIFO110243.6.5 Channel Selection110243.6.6 Sleep Mode110343.6.7 DACC Timings110343.6.8 Register Write Protection110443.7 Digital-to-Analog Converter (DACC) User Interface110543.7.1 DACC Control Register110643.7.2 DACC Mode Register110743.7.3 DACC Channel Enable Register111143.7.4 DACC Channel Disable Register111243.7.5 DACC Channel Status Register111343.7.6 DACC Conversion Data Register111443.7.7 DACC Interrupt Enable Register111543.7.8 DACC Interrupt Disable Register111643.7.9 DACC Interrupt Mask Register111743.7.10 DACC Interrupt Status Register111843.7.11 DACC Analog Current Register111943.7.12 DACC Write Protection Mode Register112043.7.13 DACC Write Protection Status Register112144. Electrical Characteristics112244.1 Absolute Maximum Ratings112244.2 Recommended Opeating Conditions112244.3 DC Characteristics112344.4 Power Consumption112944.4.1 Backup Mode Current Consumption112944.4.1.1 Configuration A: Embedded Slow Clock RC Oscillator Enabled112944.4.1.2 Configuration B: 32768 kHz Crystal Oscillator Enabled112944.4.2 Sleep and Wait Mode Current Consumption113144.4.2.1 Sleep Mode113144.4.2.2 Wait Mode113744.4.3 Active Mode Power Consumption113944.4.3.1 SAM4S4/2 Active Power Consumption114044.4.3.2 SAM4S16/S8 Active Power Consumption114044.4.3.3 SAM4SD32/SD16/SA16 Active Power Consumption114244.4.4 Peripheral Power Consumption in Active Mode114344.5 Oscillator Characteristics114444.5.1 32 kHz RC Oscillator Characteristics114444.5.2 4/8/12 MHz RC Oscillators Characteristics114444.5.3 32.768 kHz Crystal Oscillator Characteristics114544.5.4 32.768 kHz Crystal Characteristics114544.5.5 3 to 20 MHz Crystal Oscillator Characteristics114644.5.6 3 to 20 MHz Crystal Characteristics114744.5.7 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode114744.5.8 Crystal Oscillator Design Considerations Information114844.5.8.1 Choosing a Crystal114844.5.8.2 Printed Circuit Board (PCB)114844.6 PLLA, PLLB Characteristics114944.7 USB Transceiver Characteristics115044.7.1 Typical Connection115044.7.2 Electrical Parameters115144.7.3 Switching Characteristics115144.8 12-bit ADC Characteristics115344.8.1 ADC Power Supply115344.8.1.1 ADC Bias Current115344.8.2 External Reference Voltage115444.8.3 ADC Timings115444.8.4 ADC Transfer Function115544.8.4.1 Differential Mode115544.8.4.2 Single-ended Mode115544.8.4.3 Example of LSB Computation115644.8.5 ADC Electrical Characteristics115644.8.5.1 Gain and Offset Errors1156Differential Mode1157Single-ended Mode115844.8.5.2 ADC Electrical Performances1159Single-ended Static Performances1159Single-ended Dynamic Performances1159Differential Static Performances1159Differential Dynamic Performances115910-bit ADC Mode1159Low Voltage Supply116044.8.5.3 ADC Channel Input Impedance1160Track and Hold Time versus Source Output Impedance116144.9 12-bit DAC Characteristics116244.10 Analog Comparator Characteristics116444.11 Temperature Sensor116444.12 AC Characteristics116544.12.1 Master Clock Characteristics116544.12.2 I/O Characteristics116544.12.3 SPI Characteristics116644.12.3.1 Maximum SPI Frequency116744.12.3.2 SPI Timings116844.12.4 HSMCI Timings116844.12.5 SSC Timings116944.12.6 SMC Timings117344.12.6.1 Read Timings117344.12.6.2 Write Timings117544.12.7 USART in SPI Mode Timings117844.12.7.1 USART SPI TImings118044.12.8 Two-wire Serial Interface Characteristics118144.12.9 Embedded Flash Characteristics118345. Mechanical Characteristics118445.1 Soldering Profile119545.2 Packaging Resources119546. Errata119646.1 Errata SAM4SD32/SD16/SA16/S16/S8 Rev. A Parts119646.1.1 Flash Controller119646.1.1.1 EFC: Flash Buffer not Cleared119646.1.1.2 EFC: Code Loop Optimization Cannot Be Disabled119646.1.1.3 EFC: Erase Sector Command cannot be performed if a sub-sector is locked (ONLY in Flash Sector0 ).119646.1.2 Flash119746.1.2.1 Flash: Incorrect Flash Read May Occur Depending on VDDIO Voltage and Flash Wait State119746.1.2.2 Flash: Read Error after a GPNVM or Lock Bit Writing119746.1.3 Watchdog119746.1.3.1 Watchdog Not Stopped in Wait Mode119746.1.4 Brownout Detector119846.1.4.1 Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected119846.2 Errata SAM4S4/S2 Rev. A Parts119946.2.1 Flash Controller119946.2.1.1 EFC: Erase Sector (ES) command cannot be performed if a subsector is locked (ONLY in Flash sector 0)119946.2.2 Flash119946.2.2.1 Flash: Incorrect Flash Read May Occur Depending on VDDIO Voltage and Flash Wait State119946.2.3 Brownout Detector120046.2.3.1 Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected120047. Ordering Information120148. Revision History1205Table of Contents1223文件大小： 5.8 MB页数： 1231Language: English打开用户手册
数据表 (ATSAM4S-WPIR-RD)目录Section 13Introduction31.1 Scope31.2 References and Applicable Documents4Section 25Kit Contents52.1 Deliverables52.2 Board Specifications52.3 Electrostatic Warning6Section 37Power Up73.1 Power Up the Board73.2 Sample Code and Technical Support7Section 48Hardware84.1 Introduction84.2 Function Blocks84.2.1 Processor84.2.2 Clock Circuitry94.2.3 Reset Circuitry94.2.4 Push Button Switches94.2.5 Power Supplies94.2.6 Memory104.2.7 JTAG/ICE114.2.8 Image Sensor114.2.9 PIR sensor114.2.10 ZigBee134.2.11 LED Indicators134.2.12 LCD134.2.13 Backlight Control144.3 Connectors154.3.1 JTAG/ICE Connector154.3.2 USB Micro AB164.3.3 ZigBee Socket J5174.3.4 LCD/TSC Socket J4174.4 Schematics19Section 522Revision History225.1 Revision History22文件大小： 1.3 MB页数： 23Language: English打开用户手册
